ACPL-M72T-560E 查看數據表（PDF） - Avago Technologies

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ACPL-M72T-560E

High Speed, Low Power Digital Optocouplers with R2Coupler™ Isolation and AEC-Q100 Grade 1 Qualifi cation

Avago Technologies 

ACPL-M72T Low Power Mode Switching Specifications

Over recommended temperature (-40°C to +125°C), 3.0V ≤ VDD ≤ 5.5V. All typical specifications at +25°C and VDD = 5V

Parameter

Propagation Delay Time to

Logic Low Output[1]

Propagation Delay Time to

Logic High Output[1]

Pulse Width Distortion[2]

Propagation Delay Skew[3]

Output Rise Time

(10% – 90%)

Output Fall Time

(90% - 10%)

Common Mode Transient

Immunity at Logic High

Output[4]

Common Mode Transient

Immunity at Logic High

Output[5]

Symbol Min. Typ.

tPHL

60

tPLH

35

Max. Units

100 ns

100 ns

Test Conditions

IF=4mA, CL=15pF

Fig Note

7,8, 1,2,3

9,10,

14

PWD

tPSK

tR

25

50

ns

60

ns

10

ns

tF

10

ns

| CMH | 25

40

| CML | 25

40

kV/s Using Avago LED Driving

15 4

Circuit,

VIN=0V, R1=350+/-5% ,

R2=350+/-5%, VCM=1000V,

TA=25°C

kV/s Using Avago LED Driving

16 5

Circuit,

VIN=4.5-5.5V, R1=350+/-5% ,

R2=350, VCM=1000V, TA=25°C

Package Characteristics

All Typical at TA = 25°C.

Parameter

Symbol Min.

Typ.

Max.

Units

Test Conditions

Input-Output Momentary

VISO

Withstand Voltage

4000

Vrms

RH ≤ 50%, t = 1 min.,

TA = 25°C

Input-Output Resistance

R I-O

1014



VI-O = 500 V dc

Input-Output Capacitance

C I-O

0.6

pF

f = 1 MHz, TA = 25°C

Notes:

1. tPHL propagation delay is measured from the 50% (Vin or If ) on the rising edge of the input pulse to 0.8V on the falling edge of the VO signal. tPLH

propagation delay is measured from the 50% (Vin or If ) on the falling edge of the input pulse to the 80% level of the rising edge of the VO signal.

2. PWD is defined as |tPHL - tPLH|.

3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the

recommended operating conditions.

4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.

5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.

7

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