ACPL-M484 查看數據表（PDF） - Avago Technologies
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ACPL-M484
Avago Technologies
ACPL-M484 Datasheet PDF : 12 Pages
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Table 6. Switching Specifications
Over recommended operating conditions TA = -40° C to 105° C, VCC = +4.5 V to 30 V, IF(ON) = 4 mA to 7 mA, VF(OFF) = 0 V
to 0.8 V, unless otherwise specified. All typicals at TA = 25° C.
Parameter
Propagation Delay Time
to Logic Low Output Level
Symbol
tPHL
Min. Typ.
95
Propagation Delay Time
tPLH
85
to Logic High Output Level
Pulse Width Distortion
|tPHL - tPLH|
= PWD
Propagation Delay
Difference Between
Any 2 Parts
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Logic High Common Mode
Transient Immunity
Logic Low Common Mode
Transient Immunity
PDD
tr
tf
|CMH|
|CML|
-130
-130
6
6
30
30
Max. Units Test Conditions
Fig. Note
150 ns
150
CL = 100 pF, IF(ON) = 4 mA → VF = 0 V 5, 6, 8 6
Loaded as per Fig. 5
120 ns
120
CL = 100 pF, VF = 0 V → IF(ON) = 4 mA 5, 6, 8 6
Loaded as per Fig. 5
90 ns CL = 100 pF
9
90
Loaded as per Fig. 5
130 ns CL = 100 pF
10
130
Loaded as per Fig. 5
ns
ns
kV/µs
kV/µs
|VCM| = 1000 V, IF = 4.0 mA,
VCC = 5 V, TA = 25° C
|VCM| = 1000 V, VF = 0 V,
VCC = 5 V, TA = 25° C
5
5
9
7
9
7
Table 7. Package Characteristics
Parameter
Symbol Min.
Typ. Max. Units Test Conditions
Fig. Note
Input-Output Momentary VISO
Withstand Voltage*
Input-Output Resistance
RI-O
3750 (ACPL-M484/P484)
5000 (ACPL-W484)
1012
Vrms RH < 50%, t = 1 min.
5, 8
TA = 25° C
Ohm VI-O = 500 Vdc
5
Input-Output Capacitance CI-O
0.6
pF
f = 1 MHz, VI-O = 0 Vdc
5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable).
UVLO
Figure 10a & b show typical output waveforms during Power-up and Power-down processes.
Notes:
1. Derate total package power dissipation, PT, linearly above 70° C free-air temperature at a rate of 4.5mW/°C(ACPL-P484/W484) and linearly above
85° C free-air temperature at a rate of 0.75mW/°C(ACPL-M484).
2. Detector requires a Vcc of 4.5 V or higher for stable operation as output might be unstable if Vcc is lower than 4.5 V. Be sure to check the power
ON/OFF operation other than the supply current.
3. Duration of output short circuit time should not exceed 500 ms.
4. Input capacitance is measured between pin 1 and pin 3.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse.
7. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V.
CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V. Note:
Equal value split resistors (Rin/2) must be used at both ends of the LED.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for one second (leakage detection
current limit, II-O < = 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN
60747-5-5 Insulation Characteristics Table, if applicable.
9. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device.
10. The difference of tPLH and tPHL between any two devices under the same test condition.
11. Use of a 0.1 µF bypass capacitor connected between pins Vcc and Ground is recommended.
8
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