ACS8595 查看數據表（PDF） - Semtech Corporation
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ACS8595 Datasheet PDF : 12 Pages
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ACS8595 ATCA
Line Card Protection Switch for
SONET/SDH AdvancedTCA Systems
ADVANCED COMMUNICATIONS
FINAL
PRODUCT BRIEF
Description
Features
The ACS8595 ATCA is a highly integrated, single-chip
solution for “Hit-less” protection switching of SEC
(SDH/SONET Equipment Clock) + Sync clock “Groups”,
from Master and Slave SETS clock cards and a third
(Stand-by) source, for line cards/blades in a SONET or
SDH ATCA (Advanced Telecommuncications Computing
Architecture) Network Element. The ACS8595 has fast
activity monitors on the SEC clock inputs and will
implement automatic system protection switching against
the Master clock failure. The selection of the
Master/Slave input can be forced by a Force Fast Switch
pin. If both the Master and Slave input clocks fail, the
Stand-by “Group” is selected or, if no Stand-by is
available, the device enters Digital Holdover mode.
The ACS8595 can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from
the ATCA backplane into a range of spot frequencies from
2 kHz up to 311.04 MHz (up to 77.76 MHz on the
TTL/CMOS ports). The output frequency is independently
programmable on each of the six SEC output ports, so the
ACS8595 ATCA has the potential to supply simultanously
up to six different SEC frequencies, for example, to meet
the individual requirements of several Advanced
Mezzanine Cards (AMCs).
The ACS8595 has one PECL/LVDS output port and five
TTL/CMOS ports. It also provides an 8 kHz Frame Sync
and a 2 kHz Multi-Frame Sync TTL/CMOS signal output
with programmable pulse width and polarity.
The ACS8595 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
Block Diagram
SONET/SDH applications up to OC-3/STM-1 bit rates
Switches between grouped inputs (SEC/Sync pairs)
Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz
multiples up to 155.52 MHz), plus Frame Sync/Multi-
Frame Sync
Outputs: Six SEC clocks at any of several spot frequen-
cies from 2 kHz up to 77.76 MHz via the TTL/CMOS
port and up to 311.04 MHz via the PECL/LVDS port
Modes for E3/DS3 and multiple E1/DS1 rate output
clocks
Generates 8 kHz Frame Sync and 2 kHz Multi-Frame
Sync output clocks with programmable pulse width
and polarity
Frequency translation of SEC input clock to different
local line card clocks
Robust activity monitoring on all clock inputs
Supports Free-run, Locked and Digital Holdover
modes of operation
Automatic “Hit-less” source switchover on loss of
input
External force fast switch between SEC1/SEC2 inputs
Phase Build-out for output clock phase continuity dur-
ing input switchover
PLL “Locked” and “Acquisition” bandwidths individu-
ally selectable from 18, 35 or 70 Hz
Serial interface for device set-up
IEEE 1149.1 JTAG Boundary Scan is supported.
Single 3.3 V operation, 5 V I/O compatible
Operating temperature (ambient) of -40 to +85°C
Available in 100-pin LQFP package
Lead (Pb)-free version (ACS8595T), RoHS and WEEE
compliant
Figure 1 Block Diagram of the ACS8595 ATCA
3 x SEC/Sync Input Groups
SEC1 & SEC2:
TTL/PECL/LVDS,
SEC3 and all Syncs
TTL only
SEC1
Master
SYNC1
Slave
SEC2
SYNC2
SEC3
Stand-by
SYNC3
SEC Inputs:
Programmable
Frequencies
2 kHz, 4 kHz,
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
TCK
TDI
TMS
TRST
TDO
Input
SEC Port
Monitors
and
Input
Selection
Control
IEEE
1149.1
JTAG
Selector
DPLL1
DPLL2
Digital Feedback
APLL3
E1/DS1
Synthesis
Chip
Clock
Generator
TCXO or
XO
Priority Register Set
Table
MUX
2
MUX
1
APLL2
APLL 1
Output
Port
Frequency
Selection
Serial Interface
Port
SEC Outputs:
O1 (PECL/LVDS)
O2 (TTL)
O3 (TTL)
O4 (TTL)
O5 (TTL)
O6 (TTL)
Sync Outputs:
MFrSync 2 kHz (TTL)
FrSync 8 kHz (TTL)
01 TO O6:
8 kHz
1.544/2.048 MHz
3.088/4.096 MHz
6.176/8.192 MHz
12.352/16.384 MHz
6.48 MHz (not O1)
19.44 MHz
25.92 MHz
34.368 MHz
38.88 MHz
44.736 MHz
77.76 MHz
155.52 MHz (only O1)
311.04 MHz (only O1)
F8595_001BlockDia_01
Revision 2.00/October 2005 © Semtech Corp.
Page 1
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