ACS8595 查看數據表（PDF） - Semtech Corporation
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ACS8595 Datasheet PDF : 12 Pages
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ACS8595 ATCA
ADVANCED COMMUNICATIONS
Table 3 Other Pins (cont...)
FINAL
Table 3 Other Pins (cont...)
PRODUCT BRIEF
Pin No. Symbol I/O Type
Description
Pin No. Symbol I/O Type
Description
40, SEC1_POS, I PECL/LVDS Input Reference: Programmable, default
41
SEC1_NEG
19.44 MHz, PECL.
83
SDO
O
TTLD Interface Address: SPI compatible Serial
Data Output.
42, SEC2_POS, I PECL/LVDS Input Reference: Programmable, default
43
SEC2_NEG
19.44 MHz PECL.
88
O3
O TTL/CMOS Output Reference: Programmable, disabled
by default.
45
SYNC1
46
SEC1
47
SEC2
51
SYNC2
52
SEC3
54
SYNC3
59
TRST
67
TMS
68
CLKE
69
SDI
70
CSB
73
SCLK
74
PORB
76
TCK
77
TDO
78
TDI
I
TTLD (Master) Multi-Frame Sync 2 kHz Input:
Connect to 2 or 8 kHz Multi-Frame Sync
output of Master SETS.
I
TTLD (Master) Input Reference: Programmable,
default 8 kHz.
I
TTLD (Slave) Input Reference: Programmable,
default 8 kHz.
I
TTLD (Slave) Multi-Frame Sync 2 kHz: Connect to
2 or 8 kHz Multi-Frame Sync output of Slave
SETS.
I
TTLD (Stand-by) Input Reference: External stand-
by reference clock source, programmable,
default 19.44 MHz.
I
TTLD (Stand-by) Input Reference: External stand-
by 2 or 8 kHz Multi-Frame Sync clock
source.
I
TTLD JTAG Control Reset Input: TRST = 1 to
enable JTAG Boundary Scan mode. TRST =
0 is Boundary Scan stand-by mode, still
allowing normal device operation (JTAG
logic transparent). NC if not used.
I
TTLD JTAG Test Mode Select: Boundary Scan
enable. Sampled on rising edge of TCK. NC
if not used.
I
TTLD SCLK Edge Select: SCLK active edge select,
CLKE = 1, selects falling edge of SCLK to be
active.
I
TTLD Serial Interface Address: Serial Data Input.
I
TTLU Chip Select (Active Low): This pin is
asserted Low by the microprocessor to
enable the microprocessor interface.
I
TTLD Serial Data Clock. When this pin goes High
data is latched from SDI pin.
I
TTLU Power-On Reset: Master reset. If PORB is
forced Low, all internal states are reset
back to default values.
I
TTLD JTAG Clock: Boundary Scan clock input.
O TTL/CMOS JTAG Output: Serial test data output.
Updated on falling edge of TCK.
I
TTLD JTAG Input: Serial test data Input. Sampled
on rising edge of TCK.
89
O4
O TTL/CMOS Output Reference: Programmable, disabled
by default.
90
O2
O TTL/CMOS Output Reference: Programmable, default
19.44 MHz.
93
O5
O TTL/CMOS Output Reference: Programmable, disabled
by default.
94
O6
O TTL/CMOS Output Reference: Programmable, disabled
by default.
100 SONSDHB I
TTLD
SONET or SDH Frequency Select: Sets the
initial power-up state (or state after a
PORB) of the SONET/SDH frequency
selection registers, Reg. 34, Bit 2 and
Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4.
When set Low, SDH rates are selected
(2.048 MHz etc.) and when set High,
SONET rates are selected (1.544 MHz etc.)
The register states can be changed after
power-up by software.
Introduction
The ACS8595 ATCA is a Line Card Protection device
designed to complement the Semtech SETS devices
which maintain the SETS functions in both SONET and
SDH Network Elements. The ACS8595 ATCA extends this
functionality on to the Line Card, for which it has been
specifically designed. The ACS8595 ATCA uses “Hit-less”
group switching between Master and Slave inputs or a
third (Stand-by) input group, to generate and maintain
accurate and stable SEC and frame synchronization pulse
outputs for distribution on the Line Card, typically for
Advanced Mezzaninie Cards (AMCs) on AdvancedTCA
equipment.
The ACS8595 provides a simple, compact, yet flexible
solution, which can be easily tailored for use with a range
of transmission formats and rates, via software
configuration.
The ACS8595 employs various mechanisms to maintain
the integrity of its output clocks when its input clocks fail
or fall below the required specification levels. By
smoothing out the effects of these input anomalies, the
ACS8595 improves the overall stability and reliability of
Revision 2.00/October 2005 © Semtech Corp.
Page 3
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