ACS8595 查看數據表（PDF） - Semtech Corporation
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ACS8595 Datasheet PDF : 12 Pages
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ACS8595 ATCA
ADVANCED COMMUNICATIONS
FINAL
PRODUCT BRIEF
the downstream system synchronization, which
Input frequencies supported range from 2, 4, 8 kHz (and
translates to improved quality of service.
n x 8 kHz) up to 155.52 MHz. Common E1, DS1,
The key architectural advantage that the ACS8595 has
over traditional solutions is in the use of Digital Phase
Locked Loop (DPLL) technology for precise and
repeatable performance over temperature or voltage
variations and between parts.
OC-3/STM-1 and sub-divisions are supported as spot
frequencies to which the DPLLs will directly lock. Any input
frequency, up to 100 MHz, that is a multiple of 8 kHz can
also be locked to via a built-in programmable divider.
Refer to Table 4 for details of each input port.
Semtech can provide an Evaluation Board so that
designers can rapidly appraise the ACS8595 ATCA device
and see for themselves the benefits that a Semtech ATCA
solution can bring to their designs.
Input Locking Frequency Modes
Each input port has to be configured to receive the
expected input frequency. To achieve this, three Input
Locking Frequency Modes are provided: Direct Lock,
Lock8K and DivN.
General Description
SEC Activity Monitors
Inputs
The ACS8595 SETS device has input ports for clock
groups from three sources, typically Master, Slave and
Stand-by, where each clock group comprises one SEC and
optionally one Sync signal. This means that when any SEC
input changeover is made, the corresponding Sync signal
changeover is also made. Master and Slave SEC inputs to
the device support TTL/CMOS and PECL/LVDS. The
Stand-by SEC and three Sync inputs are TTL/CMOS only.
All the TTL/CMOS ports are 3 V and 5 V compatible (with
clamping if required by connecting the VDD5V pin).
A monitoring function constantly appraises the activity of
each input SEC, and reports anomalous behavior. Each of
the input monitors is individually configurable, allowing
flags or interrupts to be raised which can influence both
the operating state of the device, and which inputs are
available for selection by the PLL circuitry. Any Input SEC
which suffers a loss-of-activity will be declared as
unavailable.
Anomalies detected by the Activity Monitor are integrated
in a Leaky Bucket Accumulator. Occasional anomalies do
not cause the accumulator to cross the alarm setting
threshold, so the selected reference source is retained.
Table 4 Input Reference Source Selection and Priority Table
Port Name
SEC1 TTL
SEC2 TTL
SEC1 DIFF
SEC2 DIFF
SYNC1
SYNC2
SEC3
SYNC3
Channel Number Input Port Technology
0011
TTL/CMOS
0100
TTL/CMOS
0101
0110
0111
1000
1001
PECL/LVDS
PECL default
PECL/LVDS
PECL default
TTL/CMOS
TTL/CMOS
TTL/CMOS
1010
TTL/CMOS
Frequencies Supported
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
2/4/8 kHz auto-sensing
2/4/8 kHz auto-sensing
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
2/4/8 kHz auto-sensing
Default Priority
2
3
0
0
n/a
n/a
4
n/a
Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being
77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 bit 2, ip_sonsdhb).
(ii) PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz (and 311.04 MHz for Output O1 only).
(iii) SEC1 TTL and SEC2 TTL ports are on pins SEC1 and SEC2. SEC1 DIFF (Differential) port uses pins SEC1POS and SEC1NEG, similarly
SEC2DIFF uses pins SEC2POS and SEC2NEG.
Revision 2.00/October 2005 © Semtech Corp.
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