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ACS8595

Line Card Protection Switch for SONET/SDH AdvancedTCA Systems

Semtech Corporation 

ACS8595 ATCA

ADVANCED COMMUNICATIONS

FINAL

PRODUCT BRIEF

Persistent anomalies cause the alarm setting threshold to the Register Descriptions in the datasheet for advanced

be crossed and result in the selected SEC (and Sync)

being rejected.

There is one Leaky Bucket Accumulator per SEC input.

Each Leaky Bucket Accumulator can be programmed with

a Bucket ID (0 to 3) which assigns to the Leaky Bucket the

features and more information.

DPLL1 Main Features

z Multiple E1 and DS1 outputs supported

z Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs

corresponding Leaky Bucket Configuration (from four

available Configurations). Each Leaky Bucket

Configuration comprises the following programmable

parameters:

z Bucket size

z Multiple phase loss and multiple phase detectors

z Direct PLL locking to common SONET/SDH input

frequencies or any multiple of 8 kHz

z Automatic mode switching between Free-run, Locked

and Digital Holdover modes (states)

z Alarm trigger (set threshold)

z Fast detection on input failure and entry into Digital

z Alarm clear (reset threshold)

z Leak rate (decay rate

Phase Locked Loops (PLLs)

Figure 1 shows the PLL circuitry which comprises two

Digital PLLs (DPLL1 and DPLL2), two output multiplying

and filtering Analog PLLs (APLL1 and APLL2), output

frequency dividers in an Output Port Frequency Selection

block, a Synthesis block, multiplexers MUX1 and MUX2,

Holdover mode (holds at the last good frequency

value)

z Frequency translation between input and output rates

via direct digital synthesis

z High accuracy digital architecture for stable PLL

dynamics combined with an APLL for low jitter final

output clocks

z Non-revertive mode

z Frame Sync pulse alignment

and a feedback Analog PLL (APLL3). These functional

blocks and their interconnections are highly configurable,

via register control, providing a range of output

frequencies and a choice of levels of jitter performance.

z Selectable automatic DPLL bandwidth control (auto

selects either Locked bandwidth, or Acquisition

bandwidth), or Locked DPLL bandwidth

z Two programmable bandwidth controls:

The DPLLs give a stable and consistent level of

performance that can be easily programmed for different

dynamic behavior or operating range. They are not

affected by operating conditions or silicon process

variations. Digital Synthesis is used to generate all

required SONET/SDH output frequencies. The digital logic

operates at 204.8 MHz that is multiplied up from the

external 12.800 MHz oscillator module. Hence the best

resolution of the output signals from the DPLLs is one

204.8 MHz cycle or 4.9 ns.

• Locked bandwidth: 18, 35 or 70 Hz

• Acquisition bandwidth: 18, 35 or 70 Hz

z Programmable damping factor, (For optional faster

locking and peaking control) Factors = 1.2, 2.5, 5, 10

or 20

z Programmable DPLL pull-in frequency range

z Phase Build-out on source switching (hit-less source

switching), on/off

z Freeze Phase Build-out, on/off

Both of the DPLLs’ outputs can be connected to

multiplying and filtering APLLs. The outputs of these

APLLs are divided making a number of frequencies

simultaneously available for selection at the output clock

ports. The various combinations of DPLL, APLL,

Multiplexer and divider configurations allow for

generation of a comprehensive set of frequencies, as

listed in Table 5 and Table 6.

DPLLs

DPLL2 Main Features

The main features of DPLL2 are:

z Always locked to DPLL1

z Single programmable bandwidth control: 18, 35 or

70 Hz

z Programmable damping factor, (For optional faster

locking and peaking control) Factors = 1.2, 2.5, 5, 10

or 20.

DPLL1 is the more feature rich of the two DPLLs. The main z Digital feedback, on/off

features of the two DPLLs are summarized here. Refer to z Output frequency selection

Revision 2.00/October 2005 © Semtech Corp.

Page 5

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