ACS8595 查看數據表（PDF） - Semtech Corporation
零件编号
产品描述 (功能)
生产厂家
ACS8595 Datasheet PDF : 12 Pages
| |||
ACS8595 ATCA
ADVANCED COMMUNICATIONS
FINAL
PRODUCT BRIEF
z DS3/E3 support (44.736 MHz / 34.368 MHz)
independent of rates from DPLL1
• Low jitter E1/DS1 options independent of rates
from DPLL1
• Frequencies of n x E1/DS1 including 16 and 12 x
E1, and 16 and 24 x DS1 supported
individually selectable. Output 01 is a differential port
(pins O1POS and O1NEG), and can be selected PECL or
LVDS. All other outputs are TTL/CMOS.
Table 5 Output Port Frequencies and Technologies
Port Name
Output Port
Technology
Frequencies Supported
• Squelched (clock off)
z Can provide the source for the 2 kHz and 8 kHz
outputs available at Outputs 01 to 06
z Can use its phase detector to measure the input
phase difference between two inputs
z Selectable digital feedback, on/off
Either the software or an internal state machine controls
the operation of DPLL1. The state machine for DPLL2 is
very simple and cannot be manually/externally controlled.
One additional feature of DPLL2 is the ability to measure
a phase difference between two inputs.
O1
O2, O3, O4,
O5 and O6
FrSync
LVDS/PECL
(LVDS default)
TTL/CMOS
TTL/CMOS
MFrSync TTL/CMOS
Frequencies as per Table 6
FrSync, 8 kHz programmable pulse width and
polarity, see Reg. 7C.
MFrSync, 2 kHz programmable pulse width and
polarity, see Reg. 7C.
Table 6 Output Frequencies/Lowest Jitter Configuration
(Typical Conditions)
2 kHz
8 kHz
Frequency (MHz)
Jitter Level (typ)
rms (ps) p-p (ns)
60
0.6
60
0.6
DPLL1 always produces an output at 77.76 MHz to feed
the APLL, regardless of the frequency selected at the
output pins or the locking frequency (frequency at the
input of the Phase and Frequency Detector — PFD).
1.536
(not O5/O6)
1.544
(not O5/O6)
2.048
2.0586667
2.316
(not O5/O6)
250
1.5
150
1.0
220
1.2
150
1.0
110
0.75
DPLL2 can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies,
which cannot be easily related to 77.76 MHz. If DPLL2 is
enabled, it locks to the 8 kHz from DPLL1. This is because
all of the frequencies of operation of DPLL2 can be
divided to 8 kHz and this will ensure synchronization of
frequencies, from 8 kHz upwards, within the two DPLLs.
2.7306667
2.796
(not O5/O6)
3.088
3.728
4.096
via Digital1 or Digital2 (not O1)
4.296
(not O5/O6)
4.86
(not O5/O6)
5.728
6.144
220
110
110
110
3800
120
60
120
250
1.2
1.0
0.75
1.0
13
1.0
0.6
1.0
1.5
APLLs
6.176
6.48
150
1.0
60
0.6
There are three APLLs. APLL1 and APLL2 provide a lower
final output jitter reducing the 4.9 ns p-p jitter from the
digital down to 500 ps p-p and 60 ps rms as typical final
outputs measured broadband (from 10 Hz to 1 GHz). The
feedback APLL (APLL3) is selected by default; it provides
improved performance over the digital feedback.
Each APLL has its own divider. Each divider
simultaneously outputs a series of fixed ratios of its APLL
input. These divided outputs are available on Output Ports
O1 to O6.
8.192
8.2346667
9.264
10.922667
11.184
12.288
12.352
16.384
16.46933
17.184
18.528
19.44
21.84533
220
1.2
760
2.6
110
0.75
250
1.6
110
1.0
250
1.5
110
0.75
220
1.2
760
2.6
120
1.0
110
0.75
60
0.6
250
1.6
Outputs
The ACS8595 delivers eight output signals on the
following ports: Six clocks, one each on ports O1 to O6;
and two Sync signals, on ports FrSync and MFrSync.
Outputs O1 to O6 are independent of each other and are
22.368
24.576
24.704
25.92
32.768
34.368
37.056
110
1.0
250
1.5
110
0.75
60
0.6
220
1.2
120
1.0
110
0.75
Revision 2.00/October 2005 © Semtech Corp.
Page 6
www.semtech.com
Share Link: 