ACS8595 查看數據表（PDF） - Semtech Corporation
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ACS8595 Datasheet PDF : 12 Pages
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ACS8595 ATCA
ADVANCED COMMUNICATIONS
FINAL
PRODUCT BRIEF
Table 6 Output Frequencies/Lowest Jitter Configuration
(Typical Conditions) (cont...)
Frequency (MHz)
Jitter Level (typ)
rms (ps) p-p (ns)
replacement source is available. Digital Holdover
operates instantaneously, which means the DPLL freezes
at the frequency it was operating at the time of entering
Digital Holdover mode.
38.88
60
0.6
44.736
49.152
(O5/O6 only)
110
1.0
250
1.5
Input Selection Priorities
49.152
49.408
49.408
51.84
65.536
65.536
68.736
74.112
74.112
77.76
89.472
98.304
98.304
98.816
131.072
137.472
(O1 only)
(O5/O6 only)
(O1 only)
(O5/O6 only)
(O1 only)
(O5/O6 only)
(O1 only)
(O5/O6 only)
(O1 only)
(O1 only)
(O1 only)
(O1 only)
(O5/O6 only)
900
4.5
150
1.0
760
2.6
60
0.6
220
1.2
120
1.0
120
1.0
110
0.75
110
0.75
60
0.6
110
1.0
900
4.5
900
4.5
760
2.6
250
1.6
120
1.0
Each input SEC can be programmed with a priority
number (see Table 4) allowing references to be chosen
according to the highest priority valid input. Under normal
operation, the input SECs are selected automatically,
according to availability and in order of priority. For special
circumstances, such as chip or board testing, the
selection may be forced by configuration.
The priority table is initially defined by the default
configuration and can be changed via the Serial interface
by the Network Manager. In this way, when all the defined
sources are active and valid, the source with the highest
programmed priority is selected but, if this source fails,
the next-highest source is selected, and so on.
148.224
155.52
311.04
(O1 only)
(O1 only)
110
0.75
60
0.6
60
0.6
Table 4 gives details of the input reference ports. Specific
frequencies and priorities are set by configuration.
Modes of Operation
Ultra Fast Switching
The device has three principle modes of operation:
z Free-run
z Locked
z Digital Holdover
The Free-run mode is typically used following a power-on-
reset or a device reset before network synchronization
has been achieved. In the Free-run mode, the timing and
synchronization signals generated from the ACS8595 are
based on the 12.800 MHz clock frequency provided from
the external oscillator and are not synchronized to an
input SEC. The accuracy can be enhanced via software
calibration to within ±0.0196229 ppm.
The Locked mode is used when an input SEC has been
selected and the PLL has had time to lock. When the
Locked mode is achieved, the output signal is in phase
and is locked to the selected input SEC. The priority table
determines which input SEC is selected. When the
ACS8595 is in Locked mode, the output frequency and
phase follows that of the selected input SEC.
In Digital Holdover mode, the ACS8595 provides the
timing signals to maintain the Line Card when its currently
selected input source becomes invalid, and no other valid
SEC inputs are monitored using a leaky bucket approach
to allow source qualification criterion to be monitored. A
reference source is normally disqualified after the leaky
bucket monitor thresholds have been crossed. An option
for a faster disqualification has been implemented so that
a loss of activity of just a few reference clock cycles will
raise an alarm and cause a reference switch.
External Forced Fast Protection Switching
External Forced Fast Protection Switching mode, for fast
switching between inputs SEC1 or SEC2, can be triggered
directly from the dedicated pin SRCSW.
Restoration
Restoration of repaired reference sources is handled
carefully to avoid inadvertent disturbance of the output
clock. For this, the ACS8595 has two modes of operation;
Revertive and Non-revertive.
Sync Reference Sources
The ACS8595 provides the facility to have a Sync
reference source associated with each SEC.
Revision 2.00/October 2005 © Semtech Corp.
Page 7
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