7005 查看數據表（PDF） - Aeroflex Corporation
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7005 Datasheet PDF : 29 Pages
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1553 DATA BUS
RT ZO
2%
DIRECT-COUPLED CONFIGURATION
(SHORT-STUB)
N = 1:2.5
R1 4
0.75ZO, 2% 5
1 42 DATA
6
7
R2 8
0.75ZO, 2%
2 43 GND
3 40 DATA
N = 1.4:1
R3, 2% 1
4
0.75 ZO
5
2
6
7
R4, 2% 3
8
0.75ZO
N = 1:1.79
4
1 49 DATA
5
6
2 50 GND
7
8
3 51 DATA
RT
Zo, 2%
TRANSFORMER-COUPLED
CONFIGURATION (LONG-STUB)
+5V
+5V
38 53
87 16
D15 79
D14 78
D13 77
D12 76
D11 75
D10 74
D9 73
D8 72
ACT7005/7006
D7 71
D6 70
D5 69
D4 68
D3 67
D2 66
D1 65
D0 64
90
DS
88
RD
89
WR
84
A3
83
A2
82
A1
81
A0
U1
54LS245
11 B8
12 B7
13 B6
14 B5
15 B4
16 B3
17 B2
18 B1
9
A8
8
A7
7
A6
6
A5
5
A4
4
A3
3
A2
2
A1
A→B EN
U2
54LS245
11 B8
12 B7
13 B6
14 B5
15 B4
16 B3
17 B2
18 B1
9
A8
8
A7
7
A6
6
A5
5
A4
4
A3
3
A2
2
A1
A→B EN
TRANSCEIVER A
41 OUTPUT GND
43 ANALOG GND
44 DIGITAL GND
TRANSCEIVER B
50 OUTPUT GND
48 ANALOG GND
47 DIGITAL GND
2 LOGIC
80
INT *1 62
INT *2 63
DONE 60
SELF TEST 54
U3
54LS244
17 2A4
15 2A3
13 2A2
11 2A1
8 1A4
6 1A3
4 1A2
2 1A1
2Y4 3
2Y3 5
2Y2 7
2Y1 9
1Y4 12
1Y3 14
1Y2 16
1Y1 18
AD10 OUT 86
AD10 IN 85
28
M 16/8
31
RESET
1
CLOCK
R5
10KΩ
1G 2G
1 19
+5V
D15
D14 (MSB)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DS (Device Select)
RD (Read from RT/BC)
WR (Write to RT/BC)
A3 (MSB)
A2
A1
A0 (LSB)
GOOD BLOCK(RT)/VALID(BC)
VALID TRANS(RT)/INVALID(BC)
DONE
SELF-TEST
These are the recommended
interrupts, but use of them is
optional. The user can select any
combination of interrupts
depending on the needs of the
RT/BC. In addition to the 4
interrupts above, the user can
select from among 8 others to suit
the RT/BC needs.
Master Reset
6MHz Clock
5 Bit RT Address and
Parity Bit. These lines
can be hardwired for an
RT address or they can
be set by jumpers, DIP
switches, or
TTL/CMOS latches.
Figure 3 – Typical Interface Connections
Aeroflex Circuit Technology
7
SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700
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