AD1881 查看數據表（PDF） - Analog Devices
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AD1881 Datasheet PDF : 22 Pages
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- ANALOGDEVICESFAX-ON-DEHANHDOTLINE Page 1~
AD1881
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Paratneter
Symbol
.MiD Typ
Max Units
RESET Active Low Pulsewidth
tRST_LOW
50
TIS
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
tRST2CLK
833
fJS
tSC_HIGH
80
TIS
tSc_LOW
19.5
fJS
SYNC Inactive to BIT_CLK Startup Delay
tSC2CUZ
162.8
TIS
BIT_CLK Frequency
12.288
l\1Hz
BIT_CLK Period
tCLK_PDRIOD
81.4
TIS
BIT_CLK Output Jitter!
750 ps
BIT_CLK High Pulsewidth
tCLKJIIGH
36.62 40.69
44.76 TIS
BIT_CLK Low Pulsewidth
tCLK_LOW
36.62 40.69
44.76 TIS
SYNC Frequency
48.0
kHz
OBSOLETE SYNC Period
Setup to Falling Edge ofBIT_CLK
Hold from Falling Edge of BIT - CLK
BIT_CLKRise Time
BIT_CLKFall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN
SDATA_IN
SDATA_Our
SDATA_Our
Rise Time
Fall Time
Rise Time
Fall TIme
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OlIT)
Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
Propagation Delay
NOTES
'Output jitter is directly dependent on crystal input jitter.
Specifications subject to eh3Ilge WitilOut notice.
tSC]ERIOD
20.8
fJS
tSETUP
5
liS
tHoLD
5
liS
tRISECUZ
2
4
10
ns
tFM.LCUZ
2
4
10
ns
tRISESC
2
4
10
ns
tFM.LSC
tRISEDN
2
4
2
4
10
ns
10
ns
tFM.LDN
2
4
10
ns
tRISEDOUT
2
4
10
ns
tFM.LDOUT
2
4
10
ns
tS2_PDO
0
tSETUP2RST
15
10
ms
TIS
toFF
25
TIS
15
TIS
REV. 0
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