AD1881 查看數據表（PDF） - Analog Devices

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AD1881

AC'97 SoundMAX® Codec

Analog Devices 

- ANALOGDEVICESfAX-ON-DEHANDHOTLINE Page 15

AD1881

""'" --i

BILCLK

1 .. tRST.LOW ~*4- ~12CLJ(

flJ1JU1f

Figure 1. Cold Reset

~ BIT CLK

tRI~ 1- -J ~LK

SYNC~

tRlS~ 1- -J 1- tFALlSYNC

SDATIAN ~

tRI~ 1- -j ~;ALLDIN

SYNC JtSVNC.I-UGH-{tRS12CLK1

BIT.CLK

n..rIJlJl.f

SDATOAUT~

~S~

1- -j ~OUT

Figure 2. Warm Reset

Figure 5. Signal Rise and Fall Time

BIT_CLK

tcuc.LOW

OBS::: SYNC

LOW

g-

tSVNC_HGH

tsVNC_PERlOO

OL ~ Figure 3. Clock Timing

Tl- ETE ,~

SYNC

BIT.CLK

SDATA_OUT

tS2_POOWN

SDATA.IN

NOTE: BIT.CLK NOT TO SCALE

Figure 6. AC Link Low Power Mode Timing

RESET

BIT.CLK

SYNC

tg

fL

SDATA.OUT

SDATA_OUT

tHoLD

Figure 4. Data Setup and Hold

SDATA_IN, BIT _CLK

HI-Z

Figure 7. A TE Test Mode

-6-

REV. 0

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