AD1882 查看數據表（PDF） - Analog Devices
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AD1882 Datasheet PDF : 16 Pages
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AD1882
Table 4. AD1882 General Specifications (Continued)
Parameter
Min
Typ
Max
Unit
Digital GPIO Pins: GPIO_0, GPIO_1/EAPD
Input Signal High (VIH)
Input Signal Low (VIL)
DVIO × 0.60
0
DVIO
V
DVIO × 0.24 V
Input Leakage Current (Signal High, (IIH)
Input Leakage Current (Signal Low, (IIL)
Output Signal High (VOH)
Output Signal Low (VOL)
IOUT = –500 μA
IOUT = +1500 μA
150
50
DVIO × 0.72
0
nA
μA
DVIO
V
DVIO × 0.10 V
S/PDIF_OUT
Output Signal High (VOH)
IOUT = –500 μA
DVIO × 0.72
DVIO
V
Output Signal Low (VOL)
Power Supply
IOUT = +1500 μA
Analog (AVDD) 3.3 V ± 5%
Power Supply Range
Power Dissipation
Supply Current
E Digital (DVDD) 3.3 V ± 10%
Power Supply Range
Power Dissipation
T Supply Current
Digital I/O (DVIO) 3.3 V ± 10%
Power Supply Range
Power Dissipation
E Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1
1 Guaranteed but not tested.
2 Measurements reflect main ADC.
L 3 RMS values assume sine wave input.
HD AUDIO LINK SPECIFICATIONS
HD Audio signals comply with the High Definition Audio spec-
O ifications. Please refer to these specifications at
www.intel.com/standards/hdaudio.
POWER-DOWN STATES
S Table 5. Power-Down States
Parameter
B Function Node In D0, All Nodes Active
Function Node in D3
Codec in RESET
Individual block power savings
O DAC Pair Powered Down Saves (Each)
0
DVIO × 0.10
3.13
3.30
3.46
116
35
2.97
3.30
3.63
162
49
2.97
3.30
3.63
3.96
1.20
80
IDVDD Typ
49
16
3
6
IAVDD Typ
35
0.7
3
6
Unit
mA
mA
mA
mA
V
V
mW
mA
V
mW
mA
V
mW
mA
dB
ADC Pair Powered Down Saves (Each)
5
4.4
mA
Mixer Power Control (and Associated Amps) Saves
0
3
mA
MIC_BIAS Powered Down Saves1
0
1.0
mA
1 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The
0 Ω and high-Z states remain unaffected by the MIC_BIAS power state.
Rev. A | Page 6 of 16 | April 2008
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