AD1882A 查看數據表（PDF） - Analog Devices
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AD1882A Datasheet PDF : 20 Pages
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AD1882A
Table 6. AD1882A Pin Descriptions
Mnemonic
Pin No. Function
Description
DIGITAL INTERFACE
SDATA_OUT
5
I
Link Serial Data Output. AD1882A input stream. Clocked on both edges of the
BIT_CLK.
BIT_CLK
6
I
Link Bit Clock. 24.000 MHz serial data clock.
SDATA_IN
8
I/O
Link Serial Data Input. AD1882A output stream clocked only on one edge of BIT_CLK.
SYNC
10
I
Link Frame Sync.
RESET
11
I
Link Reset. AD1882A master hardware reset
DIGITAL I/O
GPIO_0
2
I/O
General-Purpose Input/Output. Supports S/PDIF output as primary function.
GPIO_1/EAPD
47
I/O
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
circuitry. By default pin is in a high-Z state. When used as EAPD: high-Z = amp-on,
S/PDIF_OUT
48
O
DVSS = amp off.
S/PDIF output.
DM_DATA
45
I
Digital Microphone Data Input. Support for 2 digital microphones
DM_CLK
46
O
Digital Microphone Clock Output.
JACK SENSE AND EAPD
SENSE_A/SRC_B
13
I/O
JACK SENSE A-D Input/Sense B Drive.
SENSE_B/SRC_A
34
I/O
JACK SENSE E-H Input/Sense A Drive.
ANALOG I/O
PCBEEP
12
LI
Monaural Input from System for Analog PCBeep.
PORT-E_L
14
LI, MIC, LO, SWAP Auxiliary Input/Output Left Channel.
PORT-E_R
15
LI, MIC, LO, SWAP Auxiliary Input/Output Right Channel.
PORT-F_L
16
I/O
Auxiliary Input/Output Left Channel.
PORT-F_R
17
I/O
Auxiliary Input/Output Right Channel.
CD_L
18
LI
CD Audio Left Channel.
CD_GND
19
LI
CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to
AGND via 0.1 μF capacitor if not in use as CD_GND.
CD_R
20
LI
CD Audio Right Channel.
PORT-B_L
21
LI, MIC, HP, LO Front Panel Stereo MIC/Line-In.
PORT-B_R
22
LI, MIC, HP, LO Front Panel Stereo MIC/Line-In.
PORT-C_L
23
LI, MIC, LO
Rear Panel Stereo MIC/Line-In.
PORT-C_R
24
LI, MIC, LO
Rear Panel Stereo MIC/Line-In.
PORT-D_L
35
LI, HP, LO
Rear Panel Headphone/Line-Out.
PORT-D_R
36
LI, HP, LO
Rear Panel Headphone/Line-Out.
PORT-A_L
39
LI, MIC, HP, LO Front Panel Headphone/Line-Out.
MONO_OUT
40
LO
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
PORT-A_R
41
LI, MIC, HP, LO Front Panel Headphone/Line-Out.
PORT-G_L
43
LO, SWAP
Rear Panel C/LFE Output.
PORT-G_R
44
LO, SWAP
Rear Panel C/LFE Output.
FILTER/REFERENCE
MIC_BIAS-B
28
O
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
MIC_BIAS-C
29
O
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
MIC_BIAS-E
31
O
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
DVCORE
1
O
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
VREF_FLT
27
O
parallel between Pin 1 and DVSS (Pin 4).
Voltage Reference Filter. This pin must be connected to filter caps: 1.0 μF and 0.1μF
connected in parallel between Pin 27 and AVSS (Pins 26, 42).
The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving
headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically
used to support C/LFE or shared C/LFE function).
Rev. 0 | Page 9 of 20 | August 2008
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