AD1884 查看數據表（PDF） - Analog Devices
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AD1884 Datasheet PDF : 16 Pages
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AD1884
Table 3. AD1884 Pin Descriptions
Mnemonic
Pin No.
I/O
Description
DIGITAL INTERFACE
SDATA_OUT
5
BIT_CLK
6
SDATA_IN
8
SYNC
10
RESET
11
DIGITAL I/O
GPIO_2
30
GPIO_1/MIC_BIAS-E 31
GPIO_0/EAPD
47
S/PDIF_OUT
48
JACK SENSE AND EAPD
SENSE_A/SRC_B
13
SENSE_B/SRC_A
34
ANALOG I/O
PCBEEP
12
Port E_L
14
Port E_R
15
Port F_L
16
Port F_R
17
CD_GND
19
I
Link Serial Data Output. AD1884 input stream. Clocked on both edges of the
BIT_CLK.
I
Link Bit Clock. 24.000 MHz serial data clock .
I/O
Link Serial Data Input. AD1884 output stream clocked only on one edge of BIT_CLK.
I
Link Frame Sync.
I
Link Reset. AD1884 master hardware reset.
I/O
General Purpose I/O/Microphone Bias for Port E. Capable of Hi-Z, 1.65 V, and 2.86 V.
I/O
Pin 31 shares functionality between GPIO_1 and MIC_BIAS_E. These functions are
mutually exclusive.
I/O
EAPD/General Purpose Input/Output pin. Pin 47 shares functionality between
GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function
takes priority over the GPIO function. By default, the pin is in a Hi-Z state. External
resistors should be used to insure the proper circuit state when this pin is in Hi-Z.
O
S/PDIF_OUT – Supports S/PDIF output.
I/O
Jack Sense A-D Input/Sense B drive.
I/O
Jack Sense E-F Input/Sense A drive.
LI
Monaural Input from system for Analog PCBeep.
LI, MIC, LO Auxiliary Input/Output Left Channel.
LI, MIC, LO Auxiliary Input/Output Right Channel.
LI, LO Auxiliary Input/Output Left Channel.
LI, LO Auxiliary Input/Output Right Channel.
I
CD-Audio-Analog-Ground-Reference. Must be connected to AGND via a 0.1 μF
capacitor if not in use as CD_GND. MUST always be ac-coupled.
Port B_L
21
Port B_R
22
Port C_L
23
Port C_R
24
MONO_OUT
32
Port D_L
35
Port D_R
36
Port A_L
39
Port A_R
41
FILTER/REFERENCE
VREF _FILT
27
MIC_BIAS-B
28
MIC_BIAS-C
29
LI, MIC
LI, MIC
LI, MIC
LI, MIC
LO
HP, LO
HP, LO
HP, LO
HP, LO
O
O
O
Front Panel stereo MIC/Line-In.
Front Panel stereo MIC/Line-In.
Rear Panel stereo MIC/Line-In.
Rear Panel stereo MIC/Line-In.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Voltage Reference Filter.
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Both MIC bias pins are capable of Hi-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on
Pin 33), Hi-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33).
DVCORE
1
POWER AND GROUND
DVIO 3.3V
3
DVSS
7
DVDD 3.3 V
9
O
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator. This pin must be connected to
filter caps: 10 μf, 1.0 μf, and 0.1 μf connected in parallel between Pin 1 and
DVSS (Pin 7).
I
Link Digital I/O Voltage Reference. 3.3 V
I
Digital Supply Return (ground).
I
Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the
internal digital core internal to the AD1884.
The symbols used in this table are defined as: I = Input, O = Output, LI = Line Level Input, LO = Line Level Output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier.
Rev. 0 | Page 10 of 16 | January 2007
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