AD1896 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD1896

192 kHz Stereo Asynchronous Sample Rate Converter

Analog Devices 

AD1896

TIMING DIAGRAMS

LRCLK_I

SCLK I

SDATA I

tLRIS

tDIS

tDIH

tSIH

tSIL

LRCLK O

SCLK O

tDOPD

SDATA O

tSOH

tSOL

tDOH

LRCLK O

tLROS

tLROH

SCLK O

tTDMS

TDM IN

tTDMH

Figure 1. Input and Output Serial Port Timing (SCLK I/O,

LRCLK I/O, SDATA I/O, TDM_IN)

MCLK I

RESET

tRSTL

Figure 2. RESET Timing

tMPWH

tMPWL

Figure 3. MCLK_I Timing

–4–

REV. A

Share Link: