AD1974 查看數據表（PDF） - Analog Devices
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AD1974 Datasheet PDF : 24 Pages
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Data Sheet
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Conditions/Comments
DVDD
AVDD
MCLK = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
MCLK = 256 fS, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
AD1974
Min
Typ
Max
Unit
3.0
3.3
3.6
V
3.0
3.3
3.6
V
56
mA
65
mA
95
mA
2.0
mA
74
mA
23
mA
429
mW
185
mW
244
mW
83
mW
50
dB
50
dB
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
All modes @ 48 kHz
Factor
0.4375 fS
0.5 fS
0.5625 fS
22.9844 fS
Min Typ
Max
Unit
21
kHz
±0.015
dB
24
kHz
27
kHz
79
dB
479
µs
TIMING SPECIFICATIONS
−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK)
AND RESET
tMH
tMH
Condition
MCLK duty cycle
fMCLK
fMCLK
tPDR
tPDRR
MCLK frequency
Low
Recovery
Comments
Min Max Unit
ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS 40 60 %
ADC clock source = direct MCLK @ 512 fS (bypass
on-chip PLL)
40 60 %
PLL mode, 256 fS reference
6.9 13.8 MHz
Direct 512 fS mode
27.6 MHz
15
ns
Reset to active output
4096
tMCLK
Rev. D | Page 5 of 24
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