AD1974 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD1974 Datasheet PDF : 24 Pages
| |||
AD1974
Parameter
PLL
Lock Time
256 fS VCO Clock
Output Duty Cycle
MCLK_O Pin
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALS
tABDD
AUXILIARY INTERFACE
tXDS
tXDH
tXBH
tXBL
tXLS
tXLH
Condition
Comments
MCLK and LRCLK input
CCLK high
CCLK low
CCLK frequency
CDATA setup
CDATA hold
Setup
Hold
High
COUT enable
COUT delay
COUT hold
COUT tristate
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
AAUXDATA setup
AAUXDATA hold
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
See Figure 5
fCCLK = 1/tCCP; only tCCP shown in Figure 5
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
Not shown in Figure 5
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 5
From CCLK falling
See Figure 13
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
See Figure 12
To AUXBCLK rising
From AUXBCLK rising
To AUXBCLK rising
From AUXBCLK rising
Data Sheet
Min Max Unit
10 ms
40 60 %
35
ns
35
ns
10 MHz
10
ns
10
ns
10
ns
10
ns
10
ns
30 ns
30 ns
30
ns
30 ns
10
ns
10
ns
10
ns
5
ns
−8 +8 ns
18 ns
10
ns
5
ns
10
ns
10
ns
10
ns
5
ns
Rev. D | Page 6 of 24
Share Link: 