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AD1980 查看數據表(PDF) - Analog Devices

零件编号
产品描述 (功能)
生产厂家
AD1980
ADI
Analog Devices ADI
AD1980 Datasheet PDF : 32 Pages
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AD1980
Parameter
PR[K:I]1
POWER-DOWN STATES2
Fully Active
000
ADC
000
FRONT DAC
000
SURROUND DAC
010
CENTER/LFE DAC
101
ADC + ALL DACs
111
Mixer
000
ADC + Mixer
000
ALL DACs + Mixer
111
ADC + ALL DACs + Mixer
111
Standby
111
Headphone Standby
000
NOTES
1PR bits are controlled in Reg. 2Ah and 26h
2Values presented with VREFOUT loaded.
Specifications subject to change without notice.
PR[6:0]1
000 0000
000 0001
000 0010
000 0000
000 0000
000 0011
000 0100
000 0101
000 0110
000 0111
011 1111
100 0000
DVDD Typ
53
44
46
46
46
12
52
45
31
12
0
52
AVDD Typ
70
66
61
61
61
33
44
39
14
8
0
65
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter
CLOCK SPECIFICATIONS*
Input Clock Frequency (XTAL Mode or Clock Oscillator)
Input Clock Frequency (Reference Clock Mode)
Input Clock Frequency (USB Clock Mode)
Recommended Clock Duty Cycle
*Guaranteed but not tested.
Specifications subject to change without notice.
Min
Typ
Max
24.576
14.31818
48.000
40
50
60
Unit
MHz
MHz
MHz
%
TIMING PARAMETERS (Guaranteed over Operating Temperature Range)
Parameter
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter1, 2
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to RESET Inactive (SYNC, SDATA_OUT)
Rising Edge of RESET to Hi-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from BIT_CLK Rising
NOTES
1Guaranteed but not tested.
2Output jitter directly dependent on crystal input jitter.
Specifications subject to change without notice.
Symbol
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
Min
162.8
162.8
40
39.7
4
3
2
2
2
2
2
2
2
2
0
15
Typ
1.0
1.3
19.5
12.288
81.4
750
48.0
20.8
4
4
4
4
4
4
4
4
Max
400,000
Ϯ1.0
41.7
41.4
6
6
6
6
6
6
6
6
1.0
25
15
50
15
Unit
µs
ns
µs
µs
ns
MHz
ppm
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
–4–
REV. 0

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