AD5110 查看數據表（PDF） - Analog Devices
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AD5110 Datasheet PDF : 28 Pages
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AD5110/AD5112/AD5114
Data Sheet
Parameter
POWER SUPPLIES
Single-Supply Power Range
Logic Supply Range
Positive Supply Current
EEMEM Store Current3, 6
EEMEM Read Current3, 7
Logic Supply Current
Power Dissipation8
Power Supply Rejection3
DYNAMIC CHARACTERISTICS3, 9
Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Density
FLASH/EE MEMORY RELIABILITY3
Endurance10
Data Retention11
Symbol
IDD
IDD_NVM_STORE
IDD_NVM_READ
ILOGIC
PDISS
PSR
BW
THD
ts
eN_WB
Test Conditions/Comments Min
2.3
1.8
VDD = 5 V
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = 5 V ± 10%
RAB = 5 kΩ
RAB =10 kΩ
RAB = 80 kΩ
Code = half scale − 3 dB
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
VA = VDD/2 + 1 V rms,
VB = VDD/2, f = 1 kHz,
code = half scale
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
VA = 5 V, VB = 0 V,
±0.5 LSB error band
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
TA = 25°C
100
Typ1 Max
Unit
5.5
V
VDD
V
750
nA
2
mA
320
μA
30
nA
5
μW
−43
dB
−50
dB
−64
dB
4
MHz
2
MHz
200
kHz
−75
dB
−80
dB
−85
dB
μs
2.5
μs
3
μs
10
μs
7
nV/√Hz
9
nV/√Hz
20
nV/√Hz
1
MCycles
kCycles
50
Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 6 of 28
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