AD5121(Rev0) 查看數據表（PDF） - Analog Devices
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AD5121
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5121 Datasheet PDF : 32 Pages
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Data Sheet
AD5121/AD5141
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter1 Test Conditions/Comments
t1
VLOGIC > 1.8 V
VLOGIC = 1.8 V
t2
VLOGIC > 1.8 V
VLOGIC = 1.8 V
t3
VLOGIC > 1.8 V
VLOGIC = 1.8 V
t4
t5
t6
t7
t8 2
t9 3
t10
Min Typ Max Unit Description
20
ns
SCLK cycle time
30
ns
10
ns
SCLK high time
15
ns
10
ns
SCLK low time
15
ns
10
ns
SYNC-to-SCLK falling edge setup time
5
ns
Data setup time
5
ns
Data hold time
10
ns
SYNC rising edge to next SCLK fall ignored
20
ns
Minimum SYNC high time
50
ns
SCLK rising edge to SDO valid
500 ns
SYNC rising edge to SDO pin disable
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Refer
to
t
EEPROM_PROGRAM
and
t
EEPROM_READBACK
for
memory
commands
operations
(see
Table
6).
3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF.
Table 5. I2C Interface
Parameter1 Test Conditions/Comments
fSCL2
Standard mode
Fast mode
t1
Standard mode
Fast mode
t2
Standard mode
Fast mode
t3
Standard mode
Fast mode
t4
Standard mode
Fast mode
t5
Standard mode
Fast mode
t6
Standard mode
Fast mode
t7
Standard mode
Fast mode
t8
Standard mode
Fast mode
t9
Standard mode
Fast mode
t10
Standard mode
Fast mode
t11
Standard mode
Fast mode
t11A
Standard mode
Fast mode
Min
4.0
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
Typ Max Unit Description
100 kHz Serial clock frequency
400 kHz
µs SCL high time, tHIGH
µs
µs SCL low time, tLOW
µs
ns
Data setup time, tSU; DAT
ns
3.45 µs
0.9 µs
Data hold time, tHD; DAT
µs Setup time for a repeated start condition, tSU; STA
µs
µs Hold time (repeated) for a start condition, tHD; STA
µs
µs Bus free time between a stop and a start condition, tBUF
µs
µs Setup time for a stop condition, tSU; STO
µs
1000 ns
300 ns
Rise time of SDA signal, tRDA
300 ns
300 ns
Fall time of SDA signal, tFDA
1000 ns
300 ns
Rise time of SCL signal, tRCL
1000 ns
300 ns
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Rev. 0 | Page 9 of 32
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