AD5122ABRUZ100-RL7 查看數據表（PDF） - Analog Devices
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AD5122ABRUZ100-RL7
Analog Devices
AD5122ABRUZ100-RL7 Datasheet PDF : 32 Pages
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Data Sheet
AD5122A/AD5142A
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
fSCL2
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A
t12
tSP3
tRESET
tEEPROM_PROGRAM4
tEEPROM_READBACK
tPOWER_UP5
tRESET
Test Conditions/Comments Min
Typ Max Unit Description
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
0.1
4.0
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
0
100 kHz
400 kHz
µs
µs
µs
µs
ns
ns
3.45 µs
0.9 µs
µs
µs
µs
µs
µs
µs
µs
µs
1000 ns
300 ns
300 ns
300 ns
1000 ns
300 ns
1000 ns
300 ns
300 ns
300 ns
50 ns
10 µs
Serial clock frequency
SCL high time, tHIGH
SCL low time, tLOW
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Setup time for a repeated start condition, tSU; STA
Hold time (repeated) for a start condition, tHD; STA
Bus free time between a stop and a start condition, tBUF
Setup time for a stop condition, tSU; STO
Rise time of SDA signal, tRDA
Fall time of SDA signal, tFDA
Rise time of SCL signal, tRCL
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Fall time of SCL signal, tFCL
Pulse width of suppressed spike (not shown in Figure 3)
RESET low time (not shown in Figure 3)
15 50
7 30
75
30
ms Memory program time (not shown in Figure 3)
µs Memory readback time (not shown in Figure 3)
µs Power-on EEPROM restore time (not shown in Figure 3)
µs Reset EEPROM restore time (not shown in Figure 3)
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4 The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5 Maximum time after VDD − VSS is equal to 2.3 V.
Rev. A | Page 9 of 32
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