AD5200BRMZ50-REEL7 查看數據表（PDF） - Analog Devices
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AD5200BRMZ50-REEL7 Datasheet PDF : 16 Pages
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AD5200/AD5201–SPECIFICATIONS
AD5200
ELECTRICAL
CHARACTERISTICS
(VDD = 5 V ؎ 10%, or 3 V ؎ 10%, VSS = 0 V, VA = +VDD, VB = 0 V,
–40؇C < TA < +85؇C unless otherwise noted.)
Parameter
Symbol
Conditions
Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity 2
R-DNL
Resistor Integral Nonlinearity 2
R-INL
Nominal Resistor Tolerance 3
∆RAB
Resistance Temperature Coefficient
RAB/∆T
Wiper Resistance
RW
RWB, VA = No Connect
RWB, VA = No Connect
TA = 25°C
VAB = VDD, Wiper = No Connect
VDD = 5 V
–1 ± 0.25 +1
–2 ± 0.5 +2
–30
+30
500
50 100
LSB
LSB
%
ppm/ °C
Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
Resolution
N
Differential Nonlinearity 4
DNL
Integral Nonlinearity 4
INL
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
∆VW/∆T
VWFSE
VWZSE
Code = 80 H
Code = FF H
Code = 00 H
8
–1 ± 1/4 +1
–2 ± 1/2 +2
5
–1.5 –0.5 0
0 +0.5 +1.5
Bits
LSB
LSB
ppm/ °C
LSB
LSB
RESISTOR TERMINALS
Voltage Range 5
Capacitance 6 A, B
Capacitance 6 W
Shutdown Supply Current 7
Common-Mode Leakage
VA, B, W
CA, B
CW
IDD_SD
ICM
f = 1 MHz, Measured to GND, Code = 80 H
f = 1 MHz, Measured to GND, Code = 80 H
VDD = 5.5 V
VA = VB = VDD/2
VSS
45
VDD V
pF
60
pF
0.01 5
µA
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Input Logic High
VIH
Input Logic Low
VIL
Input Current
IIL
Input Capacitance 6
CIL
VDD = 3 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
VIN = 0 V or 5 V
2.4
2.1
5
V
0.8 V
V
0.6 V
± 1 µA
pF
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation 8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS 6,9
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ)
Resistor Noise Voltage Density
VLOGIC
VDD RANGE
VDD/SS RANGE
IDD
ISS
PDISS
PSS
VSS = 0 V
VIH = +5 V or VIL = 0 V
VSS = –5 V
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V
∆VDD = +5 V ± 10%, Code = Midscale
2.7
5.5 V
–0.3
5.5 V
± 2.3
± 2.7 V
15 40 µA
15 40 µA
0.2 mW
–0.01 0.001 +0.01 %/%
BW_10 kΩ
BW_50 kΩ
THD W
tS
eN_WB
RAB = 10 kΩ, Code = 80 H
RAB = 50 kΩ, Code = 80 H
VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 kΩ
VA = 5 V, VB = 0 V, ± 1 LSB Error Band
RWB = 5 kΩ, RS = 0
600
100
0.003
2/9
9
kHz
kHz
%
µs
nV√Hz
NOTES
1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V,
VSS = –2.7 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the A terminal. A terminal is open-circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = 5 V, VSS = 0 V.
Specifications subject to change without notice.
–2–
REV. B
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