AD5241(RevB) 查看數據表（PDF） - Analog Devices
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AD5241 Datasheet PDF : 16 Pages
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AD5241/AD5242
Pin except that SHDN Pin reacts to active low. The follow-
ing two bits are O2 and O1. They are extra programmable
logic outputs that users can use to drive other digital loads,
logic gates, LED drivers, analog switches, and the like. The
three LSBs are Don’t Care. See Figure 2.
3. After acknowledging the Instruction Byte, the last byte in
Write Mode is the Data Byte, Frame 3. Data is transmitted
over the serial bus in sequences of nine clock pulses (eight
data bits followed by an Acknowledge Bit). The transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL (Figure 2).
4. Unlike the Write Mode, the Data Byte follows immediately
after the acknowledgment of the Slave Address Byte in Read
Mode, Frame 2. Data is transmitted over the serial bus
in sequences of nine clock pulses (slightly different than the
Write Mode, there are eight data bits followed by a No
Acknowledge logic 1 Bit in Read Mode). Similarly, the transi-
tions on the SDA line must occur during the low period of
SCL and remain stable during the high period of SCL. See
Figure 3.
5. When all Data Bits have been read or written, a STOP condi-
tion is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In Write Mode, the master will pull the SDA line
high during the tenth clock pulse to establish a STOP con-
dition (see Figure 2). In Read Mode, the master will issue a
No Acknowledge for the ninth clock pulse (i.e., the SDA
line remains high). The master will then bring the SDA
line low before the tenth clock pulse, which goes high to
establish a STOP condition (see Figure 3).
A repeated Write function gives the user flexibility to update the
RDAC output a number of times after addressing and instruct-
ing the part only once. During the Write cycle, each Data Byte
will update the RDAC output. For example, after the RDAC
has acknowledged its Slave Address and Instruction Bytes, the
RDAC output will be updated. If another byte is written to the
RDAC while it is still addressed to a specific slave device with
the same instruction, this byte will update the output of the
selected slave device. If different instructions are needed, the
Write Mode has to start a whole new sequence with a new Slave
Address, Instruction, and Data Bytes transferred again. Simi-
larly, a repeated Read function of the RDAC is also allowed.
READBACK RDAC VALUE
Specific to the AD5242 dual-channel device, the channel of inter-
est is the one that was previously selected in the Write Mode.
In addition, to read both RDAC values consecutively, users
have to perform two write-read cycles. For example, users may
first specify the RDAC1 subaddress in the Write Mode (it is not
necessary to issue the Data Byte and the STOP condition), then
change to the Read Mode and read the RDAC1 value. To con-
tinue reading the RDAC2 value, users have to switch back to
the Write Mode and specify the subaddress, then switch once
again to the Read Mode and read the RDAC2 value. It is not
necessary to issue the Write Mode Data Byte or the first stop
condition for this operation. Users should refer to Figures 2 and
3 for the programming format.
MULTIPLE DEVICES ON ONE BUS
Figure 5 shows four AD5242 devices on the same serial bus.
Each has a different slave address since the state of their AD0
and AD1 Pins are different. This allows each RDAC within
each device to be written to or read from independently. The
master device output bus line drivers are open-drain pull-
downs in a fully I2C compatible interface. Note, a device will be
addressed properly only if the bit information of AD0 and
AD1 in the Slave Address Byte matches with the logic inputs at
pins AD0 and AD1 of that particular device.
MASTER
5V
RP RP
SDA SCL VDD SDA SCL VDD
AD1
AD1
AD0
AD5242
AD0
AD5242
SDA SCL
AD1
SDA
SCL
VDD SDA SCL
AD1
AD0
AD5242
AD0
AD5242
Figure 5. Multiple AD5242 Devices on One Bus
LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new
component may be optimized at another. When they operate the
same signal at two different voltages, a proper method of level-
shifting is needed. For instance, one can use a 3.3 V E2PROM
to interface with a 5 V digital potentiometer. A level-shift scheme
is needed in order to enable a bidirectional communication so
that the setting of the digital potentiometer can be stored to and
retrieved from the E2PROM. Figure 6 shows one of the tech-
niques. M1 and M2 can be N-Ch FETs 2N7002 or low threshold
FDV301N if VDD falls below 2.5 V.
VDD2 = 3.3V
RP
SDA1
SCL1
3.3V
E2PROM
RP G
S
D
M1
G
S
D
M2
VDD2 = 5V
RP RP
SDA2
5V
AD5242
SCL2
Figure 6. Level-Shift for Different Voltage Devices Operation
1
IN
VDD
MP
2
O1
O1 DATA IN FRAME 2 MN
OF WRITE MODE
VSS
Figure 7. Output Stage of Logic Output O1
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
AD5241/AD5242 feature additional programmable logic out-
puts, O1 and O2, that can be used to drive digital load, analog
switches, and logic gates. They can also be used as self-con-
tained shutdown as preset to logic 0 feature which will be
explained later. O1 and O2 default to logic 0 during power-up.
The logic states of O1 and O2 can be programmed in Frame 2
under the Write Mode (see Figure 2). Figure 7 shows the out-
put stage of O1 which employs large P and N channel MOSFETs
in push-pull configuration. As shown, the output will be equal to
VDD or VSS, and these logic outputs have adequate current driving
capability to drive milliamperes of load.
REV. B
–11–
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