AD5241(RevB) 查看數據表（PDF） - Analog Devices
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AD5241 Datasheet PDF : 16 Pages
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AD5241/AD5242
Parameter
Symbol Conditions
Min Typ1 Max
Unit
INTERFACE TIMING CHARACTERISTICS (Applies to all parts.5, 9)
SCL Clock Frequency
fSCL
tBUF Bus Free Time between
t1
STOP and START
0
400
kHz
1.3
µs
tHD; STA Hold Time (Repeated START)
t2
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU; STA Setup Time for Repeated
START Condition
t5
tHD; DAT Data Hold Time
t6
tSU; DAT Data Setup Time
t7
tR Rise Time of Both
t8
SDA and SCL Signals
After this period, the first clock 600
pulse is generated.
1.3
0.6
600
100
ns
µs
50
µs
ns
900
ns
ns
300
ns
tF Fall Time of Both SDA and SCL Signals t9
tSU; STO Setup Time for STOP Condition
t10
300
ns
NOTES
1Typicals represent average readings at 25°C, VDD = 5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.
3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 10.
4Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5Guaranteed by design and not subject to production test.
6PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8All dynamic characteristics use VDD = 5 V.
9See timing diagram for location of measured values.
Specifications subject to change without notice.
REV. B
–3–
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