AD5241BRZ10(RevD) 查看數據表（PDF） - Analog Devices
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AD5241BRZ10 Datasheet PDF : 18 Pages
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AD5241/AD5242
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS5, 7, 8
−3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS
(APPLIES TO ALL PARTS5, 9)
SCL Clock Frequency
Bus Free Time Between Stop and Start, tBUF
Symbol
BW_10 kΩ
BW_100 kΩ
BW_1 MΩ
THDW
tS
eN_WB
fSCL
t1
Conditions
Min
RAB = 10 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
RAB = 1 MΩ, code = 0x80
VA = 1 V rms + 2 V dc,
VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ± 1 LSB
error band, RAB = 10 kΩ
RWB = 5 kΩ, f = 1 kHz
Typ1 Max
650
69
6
0.005
2
14
0
400
1.3
Unit
kHz
kHz
kHz
%
µs
nV√Hz
kHz
µs
Hold Time (Repeated Start), tHD; STA
t2
Low Period of SCL Clock, tLOW
t3
High Period of SCL Clock, tHIGH
t4
Setup Time for Repeated Start Condition, tSU;STA t5
Data Hold Time, tHD; DAT
t6
Data Setup Time, tSU; DAT
t7
Rise Time of Both SDA and SCL Signals, tR
t8
After this period, the first 600
clock pulse is generated
1.3
0.6
600
100
ns
µs
50
µs
ns
900
ns
ns
300
ns
Fall Time of Both SDA and SCL Signals, tF
t9
Setup Time for Stop Condition, tSU; STO
t10
300
ns
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37.
4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design, not subject to production test.
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
8 All dynamic characteristics use VDD = 5 V.
9 See timing diagram in Figure 3 for location of measured values.
Rev. D | Page 4 of 18
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