AD5245BRJZ50-R2 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD5245BRJZ50-R2 Datasheet PDF : 20 Pages
| |||
AD5245
I2C INTERFACE
I2C-COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 45). The next byte
is the slave address byte, which consists of the 7-bit slave
address followed by an R/W bit (this bit determines whether
data is read from or written to the slave device). The AD5245
has one configurable address bit, AD0 (see Table 8).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. On the other hand, if the R/W bit is
low, the master writes to the slave device.
2. In write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is a don’t care.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap, where RWA = RWB.
This feature effectively overwrites the contents of the
register; therefore, when taken out of reset mode, the RDAC
remains at midscale.
The third MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat mode
or 0 V in potentiometer mode. It is important to note that
the shutdown operation does not disturb the contents of the
register. When brought out of shutdown, the previous setting is
applied to the RDAC. Also during shutdown, new settings can
be programmed. When the part is returned from shutdown,
the corresponding VR setting is applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
cares (see Table 8).
3. After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 45).
4. In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with write mode, in which eight
data bits are followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).
5. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a STOP
condition (see Figure 45). In read mode, the master issues a
no acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line low
before the 10th clock pulse, which goes high to establish a
STOP condition (see Figure 46).
A repeated write function gives the user flexibility to update
the RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC
has acknowledged its slave address and instruction bytes in
the write mode, the RDAC output updates on each successive
byte. If different instructions are needed, then the write/read
mode has to start again with a new slave address, instruction,
and data byte. Similarly, a repeated read function of the
RDAC is also allowed.
Rev. B | Page 16 of 20
Share Link: 