AD5258 查看數據表（PDF） - Analog Devices
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AD5258 Datasheet PDF : 24 Pages
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AD5258
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
fSCL
tBUF Bus Free Time between STOP and START t1
tHD;STA Hold Time (Repeated START)
t2
0
1.3
After this period, the first clock pulse is 0.6
generated.
400 kHz
µs
µs
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU;STA Setup Time for Repeated START
t5
Condition
1.3
µs
0.6
µs
0.6
µs
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at Power On1
t6
0
0.9 µs
t7
100
ns
t8
300 ns
t9
300 ns
t10
0.6
µs
tEEMEM_STORE
26
ms
tEEMEM_RESTORE1 VDD rise time dependant. Measure
300
µs
without decoupling capacitors at VDD and
GND.
EEPROM Data Restoring Time upon Restore
Command1
EEPROM Data Rewritable Time2
FLASH/EE MEMORY RELIABILITY
Endurance3
Data Retention4
tEEMEM_RESTORE2 VDD = 5 V.
tEEMEM_REWRITE
300
540
100 700
100
µs
µs
kCycles
Years
1 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
2 Delay time after power-on PRESET prior to writing new EEPROM data.
3 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
SCL
t8
t9
t6
t2
t3
t4
t5
t7
t8 t9
SDA
t1
P
S
Figure 4. I2C Interface Timing Diagram
t10
P
Rev. 0 | Page 5 of 24
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