0.25
0.20
0.15
0.10
0.05
–40°C +85°C
0
–0.05
–0.10
–0.15
+25°C
–0.20
–0.25
0
8
16
24
65
40
48
56
64
CODE (Decimal)
Figure 12. R-INL vs. Code vs. Temperature
0.25
0.20
0.15
0.10
+25°C
–40°C
+85°C
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
0
8
16
24
65
40
48
56
64
CODE (Decimal)
Figure 13. R-DNL vs. Code vs. Temperature
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
FSE @ VDD = 5.5V
–0.35
–0.40
FSE @ VDD = 2.7V
–0.45
–0.50
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 14. Full-Scale Error vs. Temperature
AD5258
0.50
0.45
0.40
0.35
0.30
0.25
ZSE @ VDD = 2.7V
ZSE @ VDD = 5.5V
0.20
0.15
0.10
0.05
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 15. Zero-Scale Error vs. Temperature
1
VDD = 5.5V
0.1
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 16. Supply Current vs. Temperature
6
5
VDD = 5.5V
4
3
2
1
VDD = 2.7V
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 17. Logic Supply Current vs. Temperature vs. VDD
Rev. 0 | Page 9 of 24