AD5259BRMZ10 查看數據表（PDF） - Analog Devices
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AD5259BRMZ10 Datasheet PDF : 24 Pages
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AD5259
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VBB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min Typ Max Unit
I2C INTERFACE TIMING
CHARACTERISTICS1
SCL Clock Frequency
fSCL
tBUF Bus Free Time Between Stop
t1
and Start
0
400 kHz
1.3
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
0.6
μs
generated.
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU;STA Setup Time for Repeated
t5
Start Condition
1.3
μs
0.6
μs
0.6
μs
tHD;DAT Data Hold Time
t6
tSU;DAT Data Setup Time
t7
tF Fall Time of Both SDA and
t8
SCL Signals
0
0.9 μs
100
ns
300 ns
tR Rise Time of Both SDA and
t9
SCL Signals
300 ns
tSU;STO Setup Time for Stop Condition t10
0.6
μs
EEPROM Data Storing Time
tEEMEM_STORE
26
ms
EEPROM Data Restoring Time at
tEEMEM_RESTORE1 VDD rise time dependent. Measure without
300
μs
Power On2
decoupling capacitors at VDD and GND.
EEPROM Data Restoring Time upon
Restore Command2
tEEMEM_RESTORE2 VDD = 5 V.
300
μs
EEPROM Data Rewritable Time3
tEEMEM_REWRITE
540
μs
FLASH/EE MEMORY RELIABILITY
Endurance4
Data Retention5
100 700
100
kCycles
Years
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
SCL
t2
SDA
t1
P
S
t8
t6
t9
t3
t4
t7
t8
t9
t2
t5
S
Figure 4. I2C Interface Timing Diagram
t10
P
Rev. A | Page 5 of 24
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