AD5263BRUZ200 查看數據表（PDF） - Analog Devices
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AD5263BRUZ200
Analog Devices
AD5263BRUZ200 Datasheet PDF : 28 Pages
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AD5263
TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VBB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Reset Pulse Width
I2C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
tBUF Bus Free Time Between Stop and Start
tHD;STA Hold Time (Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for Stop Condition
Symbol Conditions
Min
Specifications apply to all parts2, 3
fCLK
tCH, tCL Clock level high or low
20
tDS
10
tDH
10
tCSS
15
tCSW
20
tCSH0
0
tCSH1
0
tCS1
10
tRS
5
Specifications apply to all parts2, 3
fSCL
t1
1.3
t2
After this period, the first clock
0.6
pulse is generated.
t3
1.3
t4
0.6
t5
0.6
t6
t7
100
t8
t9
t10
0.6
Typ 1
Max Unit
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
400 kHz
μs
μs
μs
50
μs
μs
0.9 μs
ns
300 ns
300 ns
μs
1 Typicals represent average readings at +25°C and VDD = +5 V, VSS = −5 V
2 Guaranteed by design and not subject to production test.
3 See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using VL = 5 V.
Rev. A | Page 5 of 28
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