AD5313R 查看數據表（PDF） - Analog Devices
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AD5313R Datasheet PDF : 28 Pages
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Data Sheet
AD5313R
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
33
16
16
15
5
5
15
20
t9
16
t10
25
t11
30
t12
20
t13
30
t14
30
Power-Up Time 4.5
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
Unit Description
20
ns SCLK cycle time
10
ns SCLK high time
10
ns SCLK low time
10
ns SYNC to SCLK falling edge setup time
5
ns Data setup time
5
ns Data hold time
10
ns SCLK falling edge to SYNC rising edge
20
ns Minimum SYNC high time (update single channel or both
channels)
10
ns SYNC falling edge to SCLK fall ignore
15
ns LDAC pulse width low
20
ns SCLK falling edge to LDAC rising edge
20
ns SCLK falling edge to LDAC falling edge
30
ns RESET minimum pulse width low
30
ns RESET pulse activation time
4.5
µs Time that is required to exit power-down mode and enter the
normal mode of operation; 24th clock edge to 90% of DAC
midscale value with output unloaded
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
SCLK
SYNC
SDIN
LDAC1
t9
t8
t4
DB23
t6
t5
LDAC2
RESET
t13
VOUTX
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3
t2
t7
DB0
t12
t10
t11
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 28
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