AD5313RBCPZ-RL7 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD5313RBCPZ-RL7 Datasheet PDF : 28 Pages
| |||
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5313R
VOUTA 1
GND 2
VDD 3
NC 4
AD5313R
12 SDIN
11 SYNC
10 SCLK
9 VLOGIC
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
2. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
Figure 6. 16-Lead LFCSP Pin Configuration
VREF 1
NC 2
16 RSTSEL
15 RESET
VOUTA 3
GND 4
VDD 5
NC 6
VOUTB 7
SDO 8
14 SDIN
AD5313R 13 SYNC
TOP VIEW
(Not to Scale) 12 SCLK
11 VLOGIC
10 GAIN
9 LDAC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
LFCSP TSSOP Mnemonic
1
3
VOUTA
2
4
GND
3
5
VDD
4
6
5
7
6
8
NC
VOUTB
SDO
7
9
LDAC
8
10
9
11
10
12
11
13
12
14
13
15
GAIN
VLOGIC
SCLK
SYNC
SDIN
RESET
14
16
15
1
RSTSEL
VREF
16
2
NC
17
N/A
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the AD5313R.
Power Supply Input. The AD5313R can be operated from 2.7 V to 5.5 V. Decouple the supply with
a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
No Connect. Do not connect to this pin.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Serial Data Output. SDO can be used to daisy-chain a number of AD5313R devices together, or it
can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on
the falling edge of the clock.
LDAC can be operated in two modes: asynchronous and synchronous. Pulsing this pin low allows
either or both DAC registers to be updated if the input registers have new data; both DAC outputs
can be updated simultaneously. This pin can also be tied permanently low.
Gain Select. When this pin is tied to GND, both DACs output a span from 0 V to VREF. If this pin is tied
to VLOGIC, both DACs output a span of 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to
VLOGIC powers up both DACs to midscale.
Reference Voltage. The AD5313R has a common reference pin. When using the internal reference,
this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference output.
No Connect. Do not connect to this pin.
Exposed Pad. The exposed pad must be tied to GND.
Rev. 0 | Page 9 of 28
Share Link: 