AD5347BCP 查看數據表（PDF） - Analog Devices

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AD5347BCP

2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs

Analog Devices 

AD5346/AD5347/AD5348

AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VREFGH 1

38 PD

VREFEF 2

37 CLR

VREFCD 3

36 GAIN

VDD 4

35 WR

VREFAB 5

34 RD

VOUTA 6

10-BIT 33 CS

VOUTB 7 AD5347 32 DB9

VOUTC

8

TOP VIEW 31

(Not to Scale)

DB8

VOUTD 9

30 DB7

AGND 10

29 DB6

VOUTE 11

VOUTF 12

VOUTG 13

VOUTH 14

DGND 15

28 DB5

27 DB4

26 DB3

25 DB2

24 DB1

BUF 16

LDAC 17

23 DB0

22 DGND

A0 18

21 DGND

A1 19

20 A2

40 39 38 37 36 35 34 33 32 31

VOUTA 1

VOUTB 2

VOUTC 3

VOUTD 4

AGND 5

AGND 6

VOUTE 7

VOUTF 8

VOUTG 9

VOUTH 10

10-BIT

AD5347

TOP VIEW

(Not to Scale)

30 RD

29 CS

28 DB9

27 DB8

26 DB7

25 DB6

24 DB5

23 DB4

22 DB3

21 DB2

11 12 13 14 15 16 17 18 19 20

Figure 8. AD5347 Pin Configuration—LFCSP

Figure 7. AD5347 Pin Configuration—TSSOP

Table 6. AD5347 Pin Function Descriptions

Pin Number

TSSOP LFCSP Mnemonic Function

1

35

VREFGH

Reference Input for DACs G and H.

2

36

VREFEF

Reference Input for DACs E and F.

3

37

VREFCD

Reference Input for DACs C and D.

4

38, 39 VDD

Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package

must be at the same potential.

5

40

VREFAB

Reference Input for DACs A and B.

6–9,

11–14

1–4,

7–10

VOUTX

Output of DAC X. Buffered output with rail-to-rail operation.

10

5, 6

AGND

Analog Ground. Ground reference for analog circuitry.

15, 21–22 11,

DGND

17–18

Digital Ground. Ground reference for digital circuitry.

16

12

BUF

Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.

17

13

LDAC

Active Low Control Input. Updates the DAC registers with the contents of the input registers, which

allows all DAC outputs to be simultaneously updated.

18

14

A0

LSB Address Pin. Selects which DAC is to be written to.

19

15

A1

Address Pin. Selects which DAC is to be written to.

20

16

A2

MSB Address Pin. Selects which DAC is to be written to.

23–32

33

19–28

29

DB0–DB9

CS

Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits.

Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or

with RD to read back data from a DAC.

34

30

RD

Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.

35

31

WR

Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.

36

32

GAIN

Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.

37

33

CLR

Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.

38

34

PD

Power-Down Pin. This active low control pin puts all DACs into power-down mode.

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