AD6472 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD6472 Datasheet PDF : 8 Pages
| |||
AD6472
S1
S2
S3
S4
ANALOG
INPUT
INPUT
CLOCK
RXCLK
OUTPUT
DATA
RX11:RX0
tC
tCH
t CL
Figure 4. Receive Interface Timing Diagram
tOD
DATA1
Receive Interface Timing
The analog input is sampled at the rising edge of the RXCLK.
The digital data, RX11:RX0, is valid on each falling edge of
RXCLK. Figure 4 shows a three-cycle latency on the receive
data.
Table V through Table VII lists the RXCLK clock switching
specifications for various RXCLK conditions. See Table IV,
Configuration Control.
Table V. 40% to 60% Duty Cycle when the RXCLK
= 1168 ÷ 2 kHz
Symbol
tC
tCH
tCL
tOD
Latency
Parameter
Clock Period
Clock Pulsewidth High
Clock Pulsewidth Low
Output Delay
Pipeline Delay
Min Typ Max
1712
685
1027
8 13
33
1027
685
19
3
Units
ns
ns
ns
ns
Cycles
TX_CLK
TX_SYNC
tSU Ն 12ns
tH Ն 10ns
1
Table VI. 40% to 60% Duty Cycle RXCLK Clock
when the RXCLK = 1160 kHz
Symbol
tC
tCH
tCL
tOD
Latency
Parameter
Min Typ Max Units
Clock Period
862
Clock Pulsewidth High 342
514
Clock Pulsewidth Low 514
342
Output Delay
8 13 19
Pipeline Delay
33 3
ns
ns
ns
ns
Cycles
Table VII. 40% to 60% Duty Cycle RXCLK when the
RXCLK = 1160 ؋ 2 kHz
Symbol
tC
tCH
tCL
tOD
Latency
Parameter
Min Typ Max Units
Clock Period
431
Clock Pulsewidth High 171
257
Clock Pulsewidth Low 257
171
Output Delay
8 13 19
Pipeline Delay
33 3
ns
ns
ns
ns
Cycles
2
TX_DATA
D11
D11
MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X
X
X
X MSB D10 D9
1. THE RISING EDGE TO TX_SYNC CAN OCCUR ANYWHERE. TX_SYNC MUST BE AT LEAST ONE CLOCK CYCLE WIDE.
2. TX_SYNC FALLING EDGE MUST OCCUR AFTER THE TX_CLK RISING EDGE THAT CAPTURED THE SERIAL LSB.
THIS ENSURES CORRECT LOADING INTO THE DAC.
THE FIRST 12 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TX PATH DAC, MSB FIRST. THE NUMBER
SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS:
OUTPUT
FULL SCALE
1/2 FULL SCALE
1/2 FULL SCALE
MINUS 1LSB
ZERO
WORD
011111111111
000000000000
111111111111
100000000000
Figure 5. Transmit Interface Timing Diagram
REV. 0
–7–
Share Link: 