AD6636(Rev0) 查看數據表（PDF） - Analog Devices
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AD6636 Datasheet PDF : 72 Pages
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AD6636
GENERAL TIMING CHARACTERISTICS
Table 3. General Timing Characteristics1, 2
Parameter
CLK TIMING REQUIREMENTS
tCLK
CLKx Period (x = A, B, C, D)
tCLKL
CLKx Width Low (x = A, B, C, D)
tCLKH
CLKx Width High (x = A, B, C, D)
tCLKSKEW CLKA to CLKx Skew (x = B, C, D)
INPUT WIDEBAND DATA TIMING REQUIREMENTS
tSI
INx [15:0] to ↑CLKx Setup Time (x = A, B, C, D)
tHI
INx [15:0] to ↑CLKx Hold Time (x = A, B, C, D)
tSEXP
EXPx [2:0] to ↑CLKx Setup Time (x = A, B, C, D)
tHEXP
EXPx [2:0] to ↑CLKx Hold Time (x = A, B, C, D)
tDEXP
↑CLKx to EXPx[2:0] Delay (x = A, B, C, D)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)
tDPREQ
↑PCLK to ↑Px REQ Delay (x = A, B, C)
tDPP
↑PCLK to Px [15:0] Delay (x = A, B, C)
tDPIQ
↑PCLK to Px IQ Delay (x = A, B, C)
tDPCH
↑PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
↑PCLK to Px Gain Delay (x = A, B, C)
tSPA
Px ACK to ↑PCLK Setup Time (x = A, B, C)
tHPA
Px ACK to ↑PCLK Hold Time (x = A, B, C)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)
tPCLK
PCLK Period
tPCLKL
PCLK Low Period
tPCLKH
PCLK High Period
tDPREQ
↑PCLK to ↑Px REQ Delay (x = A, B, C)
tDPP
↑PCLK to Px [15:0] Delay (x = A, B, C)
tDPIQ
↑PCLK to Px IQ Delay (x = A, B, C)
tDPCH
↑PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
↑PCLK to Px Gain Delay (x = A, B, C)
tSPA
Px ACK to ↓PCLK Setup Time (x = A, B, C)
tHPA
Px ACK to ↓PCLK Hold Time (x = A, B, C)
MISC PINS TIMING REQUIREMENTS
tRESET
RESET Width Low
tDIRP
CPUCLK/SCLK to IRP Delay
tSS
SYNC(0, 1, 2, 3) to ↑CLKA Setup Time
tHS
SYNC(0, 1, 2, 3) to ↑CLKA Hold Time
Temp Test Level Min
Typ
Max Unit
Full
I
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
6.66
1.71
1.70
tCLK − 1.3
0.5 × tCLK
0.5 × tCLK
0.75
1.13
3.37
1.11
5.98
ns
ns
ns
ns
ns
ns
ns
ns
10.74 ns
Full
IV
1.77
Full
IV
2.07
Full
IV
0.48
Full
IV
0.38
Full
IV
0.23
Full
IV
4.59
Full
IV
0.90
3.86 ns
5.29 ns
5.49 ns
5.35 ns
4.95 ns
ns
ns
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
5.0
ns
1.7
0.5 × tPCLK
ns
0.7
0.5 × tPCLK
ns
4.72
8.87 ns
4.8
8.48 ns
4.83
10.94 ns
4.88
10.09 ns
5.08
11.49 ns
6.09
ns
1.0
ns
Full
IV
30
ns
Full
V
7.5
ns
Full
IV
0.87
ns
Full
IV
0.67
ns
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
Rev. 0 | Page 6 of 72
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