AD6652 查看數據表（PDF） - Analog Devices
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AD6652 Datasheet PDF : 76 Pages
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AD6652
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise specified.
Table 7.
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM WRITE TIMING
tSC
Control1 to ↑CLK Setup Time
tHC
Control1 to ↑CLK Hold Time
tHWR
WR(R/W) to RDY(DTACK) Hold Time
tSAM
Address/Data to WR(R/W) Setup Time
tHAM
Address/Data to RDY(DTACK) Hold Time
tDRDY
WR(R/W) to RDY(DTACK) Delay
tACC
WR(R/W) to RDY(DTACK) High Delay
MODE INM READ TIMING
tSC
Control1 to ↑CLK Setup Time
tHC
Control1 to ↑CLK Hold Time
tSAM
Address to RD(DS) Setup Time
tHAM
Address to Data Hold Time
tDRDY
RD(DS) to RDY(DTACK) Delay
tACC
RD(DS) to RDY(DTACK) High Delay
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM WRITE TIMING
tSC
Control1 to ↑CLK Setup Time
tHC
Control1 to ↑CLK Hold Time
tHDS
DS(RD) to DTACK(RDY) Hold Time
tHRW
R/W(WR) to DTACK(RDY) Hold Time
tSAM
Address/Data To R/W(WR) Setup Time
tHAM
Address/Data to R/W(WR) Hold Time
tDDTACK DS(RD) to DTACK(RDY) Delay
tACC
R/W(WR) to DTACK(RDY) Low Delay
MODE MNM READ TIMING
tSC
Control1 to ↑CLK Setup Time
tHC
Control1 to ↑CLK Hold Time
tHDS
DS(RD) to DTACK(RDY) Hold Time
tSAM
Address to DS(RD) Setup Time
tHAM
tDDTACK
Address to Data Hold Time
DS(RD) to DTACK(RDY) Delay
tACC
DS(RD) to DTACK(RDY) Low Delay
Temp Test Level
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
Full
Full
Full
Full
Full
Temp
IV
IV
IV
IV
IV
IV
Test Level
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Min
2.0
2.5
7.0
3.0
5.0
8.0
4 × tCLK
5.0
2.0
0.0
5.0
8.0
8 × tCLK
Min
2.0
2.5
8.0
7.0
3.0
5.0
8.0
4 × tCLK
5.0
2.0
8.0
0.0
5.0
8.0
8 × tCLK
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
5 × tCLK
9 × tCLK
ns
10 × tCLK
Typ
13 × tCLK
Max
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
5 × tCLK
9 × tCLK
ns
ns
ns
ns
ns
ns
ns
10 × tCLK 13 × tCLK ns
1 Specification pertains to control signals: R/W, (WR), DS, (RD), and CS.
Rev. 0 | Page 9 of 76
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