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AD6654 查看數據表(PDF) - Analog Devices

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AD6654 Datasheet PDF : 88 Pages
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AD6654
TIMING CHARACTERISTICS
Table 7.
Parameter1, 2, 3
CLK TIMING REQUIREMENTS
tCLK
CLK Period
tCLKL
CLK Width Low
tCLKH
CLK Width High
INPUT WIDEBAND DATA TIMING REQUIREMENTS
tDEXP
CLK to EXP[2:0] Delay
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)
tDPREQ
PCLK to Px REQ Delay (x = A, B, C)
tDPP
PCLK to Px[15:0] Delay (x = A, B, C)
tDPIQ
PCLK to Px IQ Delay (x = A, B, C)
tDPCH
PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
PCLK to Px Gain Delay (x = A, B, C)
tSPA
Px ACK to PCLK Setup Time (x = A, B, C)
tHPA
Px ACK to PCLK Hold Time (x = A, B, C)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)
tPCLK
PCLK Period
tPCLKL
PCLK Low Period
tPCLKH
PCLK High Period
tDPREQ
PCLK to Px REQ Delay (x = A, B, C)
tDPP
PCLK to Px[15:0] Delay (x = A, B, C)
tDPIQ
PCLK to Px IQ Delay (x = A, B, C)
tDPCH
PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
PCLK to Px Gain Delay (x = A, B, C)
tSPA
Px ACK to PCLK Setup Time (x = A, B, C)
tHPA
Px ACK to PCLK Hold Time (x = A, B, C)
MISC PINS TIMING REQUIREMENTS
tRESET
RESET Width Low
tDIRP
CPUCLK/SCLK to IRP Delay
tSSYNC
SYNC(0, 1, 2, 3) to CLK Setup Time
tHSYNC
SYNC(0, 1, 2, 3) to CLK Hold Time
Temp Test Level
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
V
Full
IV
Full
IV
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 These timing parameters are derived from the ADC ENC rate with DDC CLK driven directly from ADC DR output.
Min
5.154
5.154
5.98
1.77
2.07
0.48
0.38
0.23
4.59
0.90
5.0
1.7
0.7
4.72
4.8
4.83
4.88
5.08
6.09
1.0
30
7.5
0.87
0.67
Typ
10.85
0.5 × tCLK
0.5 × tCLK
0.5 × tPCLK
0.5 × tPCLK
Max Unit
ns
ns
ns
10.74 ns
3.86 ns
5.29 ns
5.49 ns
5.35 ns
4.95 ns
ns
ns
ns
ns
ns
8.87 ns
8.48 ns
10.94 ns
10.09 ns
11.49 ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 9 of 88

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