AD6657A 查看數據表（PDF） - Analog Devices
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AD6657A Datasheet PDF : 36 Pages
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Data Sheet
AD6657A
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Pulse Width High (tCH)2
Aperture Delay (tA)2
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)2
Pipeline Delay (Latency)
With NSR Enabled
Wake-Up Time (from Standby)3
Wake-Up Time (from Power Down)3
OUT-OF-RANGE RECOVERY TIME
Temperature Min
Typ
Max
Unit
Full
Full
40
Full
Full
Full
625
185
200
2.7
1.3
0.13
MHz
MSPS
ns
ns
ps rms
Full
3.0
4.0
4.9
ns
Full
3.1
4.0
4.9
ns
Full
−41
+6.1
+33
ps
Full
9
Cycles
Full
12
Cycles
Full
0.5
µs
Full
310
µs
Full
2
Cycles
1 Conversion rate is the clock rate after the divider.
2 See Figure 2 for details.
3 Wake-up time is dependent on the value of the decoupling capacitors.
Data Output Timing Diagram
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
CLK–
DCO+
DCO–
D10+AB (MSB)
D10–AB (MSB)
tCH
tCL
1/fS
tDCO
D10A
D10B
D10A
tSKEW
tPD
D10B D10A D10B
D10A
D10B
D10A
D10B
D10A
D10B
D10A
D10B
D0+AB (LSB)
D0–AB (LSB)
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)
Rev. A | Page 9 of 36
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