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AD6672(Rev0) 查看數據表(PDF) - Analog Devices

零件编号
产品描述 (功能)
生产厂家
AD6672
(Rev.:Rev0)
ADI
Analog Devices ADI
AD6672 Datasheet PDF : 32 Pages
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AD6672
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
0/D0−, 0/D0 + Through D9−/D10−,
D9+/D10+ to AGND
OR+/OR− to AGND
DCO+, DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for the
LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints, maximizing
the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
Airflow
Velocity
(m/sec)
32-Lead LFCSP 0
5 mm × 5 mm 1.0
(CP-32-12)
2.0
θJA1, 2
37.1
32.4
29.1
θJC1, 3
3.1
θJB1, 4
20.7
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow increases heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces—through holes, ground, and
power planes—reduces the θJA.
ESD CAUTION
Rev. 0 | Page 10 of 32

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