AD6672 查看數據表（PDF） - Analog Devices

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AD6672

IF Receiver

Analog Devices 

AD6672

MEMORY MAP REGISTER DESCRIPTION

For more information on functions controlled in Register 0x00

to Register 0x20, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

NSR Control (Register 0x3C)

Bits[7:4]—Reserved

Bits[3:1]—NSR Mode

Bits[3:1] determine the bandwidth mode of the NSR. When

Bits[3:1] are set to 000, the NSR is configured for 22% bandwidth

mode, which provides enhanced SNR performance over 22% of

the sample rate. When Bits[3:1] are set to 001, the NSR is

configured for 33% bandwidth mode, which provides enhanced

SNR performance over 33% of the sample rate.

Data Sheet

Bit 0—NSR Enable

The NSR is enabled when Bit 0 is high and disabled when Bit 0

is low.

NSR Tuning Word (Register 0x3E)

Bits[7:6]—Reserved

Bits[5:0]—NSR Tuning Word

The NSR tuning word sets the band edges of the NSR band. In

22% bandwidth mode, there are 57 possible tuning words; in

33% bandwidth mode, there are 34 possible tuning words. In

either mode, each step represents 0.5% of the ADC sample rate.

For the equations that are used to calculate the tuning word

based on the bandwidth mode of operation, see the Noise

Shaping Requantizer section.

Rev. C | Page 28 of 30

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