AD6672 查看數據表（PDF） - Analog Devices
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AD6672 Datasheet PDF : 30 Pages
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AD6672
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)1
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (NSR Disabled)
IDRVDD1 (NSR Enabled, 22% Bandwidth Mode)
IDRVDD1 (NSR Enabled, 33% Bandwidth Mode)
POWER CONSUMPTION
Sine Wave Input (DRVDD = 1.8 V, NSR Disabled)
Sine Wave Input (DRVDD = 1.8 V, NSR Enabled,
22% Bandwidth Mode)
Sine Wave Input (DRVDD = 1.8 V, NSR Enabled,
33% Bandwidth Mode)
Standby Power3
Power-Down Power
Temperature Min
Full
11
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
Full
Full
Full
Full
1.7
Full
1.7
Full
Full
Full
Full
Full
Full
Full
Full
Full
Typ
Guaranteed
±0.1
±0.12
±7
±85
0.65
1.75
5
20
0.9
1.8
1.8
136
63
89
99
358
405
423
50
5
Max
Unit
Bits
±11
+3/−6.5
±0.2
±0.3
mV
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB rms
V p-p
pF
kΩ
V
1.9
V
1.9
V
145
mA
68
mA
mA
mA
385
mW
mW
mW
mW
mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 18 for the equivalent analog input structure.
3 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
Rev. C | Page 4 of 30
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