AD6672 查看數據表（PDF） - Analog Devices
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AD6672 Datasheet PDF : 30 Pages
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Data Sheet
AD6672
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (OR+, OR−)
LVDS Data and OR Outputs
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
Temperature Min
Typ Max
CMOS/LVDS/LVPECL
Full
0.9
Full
0.3
3.6
Full
AGND
AVDD
Full
0.9
1.4
Full
10
+22
Full
−22
−10
Full
4
Full
12
15 18
Full
1.22
2.1
Full
0
0.6
Full
50
71
Full
−5
+5
Full
26
Full
2
Full
1.22
2.1
Full
0
0.6
Full
45
70
Full
−5
+5
Full
26
Full
2
Full
1.22
2.1
Full
0
0.6
Full
45
70
Full
−5
+5
Full
26
Full
5
Full
250
350 450
Full
1.15
1.25 1.35
Full
150
200 280
Full
1.15
1.25 1.35
1 Pull-up.
2 Pull-down.
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
mV
V
mV
V
Rev. C | Page 7 of 30
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