EVAL-AD7091SDZ 查看數據表（PDF） - Analog Devices
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EVAL-AD7091SDZ Datasheet PDF : 20 Pages
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Data Sheet
SPECIFICATIONS
VDD = 2.09 V to 5.25 V, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C, unless otherwise noted.
AD7091
Table 1.
Parameter
DYNAMIC PERFORMANCE1
Signal-to-Noise Ratio (SNR)2
Signal-to-Noise-and-Distortion Ratio
(SINAD)2
Total Harmonic Distortion (THD)2
Spurious-Free Dynamic Range (SFDR)2
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
Offset Error2
Gain Error2
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance3
LOGIC INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)3
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2, 3
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Normal Mode—Static4
Normal Mode—Operational
Power-Down Mode
Test Conditions/Comments
fIN = 10 kHz sine wave
VDD < 2.7 V
VDD ≥ 2.7 V
At −3 dB
At −0.1 dB
Guaranteed no missing codes to 12 bits
During acquisition phase
Outside acquisition phase
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 µA
ISINK = 200 µA
Full-scale step input
VIN = 0 V
VDD = 5.25 V
VDD = 3 V
VDD = 5.25 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 100 kSPS
VDD = 5.25 V
Rev. B | Page 3 of 20
Min
Typ
Max
68
67
69
66.3
68
−86
−74
−85
−75
5
40
1.5
1.2
12
±0.6
±1
±0.3
±0.9
−8.5
±0.7
+5
±1.2
±4
1.1
0
VDD
±1
7
1
0.7 × VDD
0.3 × VDD
±1
5
VDD − 0.2
0.4
±1
5
Straight binary
650
350
1
2.09
5.25
9.3
27
9.1
28
450
554
367
442
45
0.374
8.2
Unit
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
Bits
LSB
LSB
LSB
LSB
LSB
V
µA
pF
pF
V
V
µA
pF
V
V
µA
pF
ns
ns
MSPS
V
µA
µA
µA
µA
µA
µA
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