EVAL-AD7142-1EBZ(RevA) 查看數據表（PDF） - Analog Devices
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EVAL-AD7142-1EBZ Datasheet PDF : 73 Pages
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AD7142
SPI TIMING SPECIFICATIONS (AD7142)
TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 4. SPI Timing Specifications
Parameter
Limit at TMIN, TMAX
fSCLK
5
t1
5
t2
20
t3
20
t4
15
t5
15
t6
20
t7
16
t8
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
Description
CS falling edge to first SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SDI setup time
SDI hold time
SDO access time after SCLK falling edge
CS rising edge to SDO high impedance
SCLK rising edge to CS high
CS
SCLK
SDI
SDO
t1
t2
1
t4
t5
MSB
t3
2
3
15
16
1
t8
2
15
16
LSB
t6
MSB
Figure 3. SPI Detailed Timing Diagram
t7
LSB
Rev. A | Page 6 of 72
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