AD7225KR(RevB) 查看數據表（PDF） - Analog Devices

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AD7225KR
(Rev.:RevB)

LC2MOS Quad 8-Bit DAC with Separate Reference Inputs

Analog Devices 

AD7225

CIRCUIT INFORMATION

D/A SECTION

The AD7225 contains four, identical, 8-bit voltage mode

digital-to-analog converters. Each D/A converter has a separate

reference input. The output voltages from the converters have

the same polarity as the reference voltages, allowing single sup-

ply operation. A novel DAC switch pair arrangement on the

AD7225 allows a reference voltage range from +2 V to +12.5 V

on each reference input.

Each DAC consists of a highly stable, thin-film, R-2R ladder

and eight high speed NMOS, single-pole, double-throw

switches. The simplified circuit diagram for channel A is shown

in Figure 7. Note that AGND (Pin 6) is common to all four

DACs.

Figure 7. D/A Simplified Circuit Diagram

The input impedance at any of the reference inputs is code de-

pendent and can vary from 11 kΩ minimum to infinity. The

lowest input impedance at any reference input occurs when that

DAC is loaded with the digital code 01010101. Therefore, it is

important that the reference presents a low output impedance

under changing load conditions. The nodal capacitance at the

reference terminals is also code dependent and typically varies

from 15 pF to 35 pF.

Each VOUT pin can be considered as a digitally programmable

voltage source with an output voltage of:

VOUTX = DX • VREFX

where DX is fractional representation of the digital input code

and can vary from 0 to 255/256.

The output impedance is that of the output buffer amplifier.

OP-AMP SECTION

Each voltage mode D/A converter output is buffered by a unity

gain noninverting CMOS amplifier. This buffer amplifier is ca-

pable of developing +10 V across a 2 kΩ load and can drive ca-

pacitive loads of 3300 pF.

The AD7225 can be operated single or dual supply; operating

with dual supplies results in enhanced performance in some pa-

rameters which cannot be achieved with single supply operation.

In single supply operation (VSS = 0 V = AGND) the sink capa-

bility of the amplifier, which is normally 400 µA, is reduced as

the output voltage nears AGND. The full sink capability of

400 µA is maintained over the full output voltage range by tying

VSS to –5 V. This is indicated in Figure 8.

Settling-time for negative-going output signals approaching

AGND is similarly affected by VSS. Negative-going settling-time

for single supply operation is longer than for dual supply opera-

tion. Positive-going settling-time is not affected by VSS.

Figure 8. Variation of ISINK with VOUT

Additionally, the negative VSS gives more headroom to the out-

put amplifiers which results in better zero code performance and

improved slew rate at the output, than can be obtained in the

single supply mode.

DIGITAL SECTION

The AD7225 digital inputs are compatible with either TTL or

5 V CMOS levels. All logic inputs are static protected MOS

gates with typical input currents of less than 1 nA. Internal in-

put protection is achieved by an on-chip distributed diode be-

tween DGND and each MOS gate. To minimize power supply

currents, it is recommended that the digital input voltages be

driven as close to the supply rails (VDD and DGND) as practi-

cally possible.

INTERFACE LOGIC INFORMATION

The AD7225 contains two registers per DAC, an input register

and a DAC register. Address lines A0 and A1 select which input

register will accept data from the input port. When the WR sig-

nal is LOW, the input latches of the selected DAC are transpar-

ent. The data is latched into the addressed input register on the

rising edge of WR. Table I shows the addressing for the input

registers on the AD7225.

Table I. AD7225 Addressing

A1

A0

Selected Input Register

L

L

DAC A Input Register

L

H

DAC B Input Register

H

L

DAC C Input Register

H

H

DAC D Input Register

–6–

REV. B

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