AD7228A 查看數據表（PDF） - Analog Devices
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AD7228A Datasheet PDF : 8 Pages
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AD7228A
+5 V SUPPLY OPERATION (VDD = +5 V ؎ 5%, VSS; = 0 to –5 V ؎ 10%, GND = 0 V, VREF = +1.25 V, RL = 2 k⍀, CL = 100 pF
unless otherwise noted.) AII specifications TMIN to TMAX unless otherwise noted.
Parameter
B
Version
C
Version
T
Version
U
Version
STATIC PERFORMANCE
Resolution
8
8
8
8
Relative Accuracy
±2
±2
±2
±2
Differential Nonlinearity
±1
±1
±1
±1
Full-Scale Error
±4
±2
±4
±2
Zero Code Error
@ 25°C
± 30
± 20
± 30
± 20
TMIN to TMAX
± 40
± 30
± 40
± 30
REFERENCE INPUT
Reference Input Range
1.2
1.2
1.2
1.2
1.3
1.3
1.3
1.3
Reference Input Resistance
2
2
2
2
Reference Input Capacitance
500
500
500
500
POWER REQUIREMENTS
Positive Supply Range
Positive Supply Current
@ 25°C
TMIN to TMAX
Negative Supply Current
@ 25°C
TMIN to TMAX
4.75/5.25
16
20
14
18
4.75/5.25
16
20
14
18
4.75/5.25
16
22
14
20
4.75/5.25
16
22
14
20
NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when VSS = 0 V.
Specifications subject to change without notice.
Units
Bits
LSB max
LSB max
LSB max
mV max
mV max
V min
V max
kΩ min
pF max
V min/V max
µA max
µA max
µA max
µA max
Conditions/Comments
Guaranteed Monotonic
For Specified Performance
SWITCHING CHARACTERISTICS1, 2 (See Figures 1, 2; VDD = +5 V ؎ 5% or +10.8 V to +16.5 V; VSS = 0 V or –5 V ؎ 10%)
Parameters
Limit at 25°C
All Grades
Limit at TMIN, TMAX
(B, C Versions)
Limit at TMIN, TMAX
(T, U Versions)
Units
Conditions/Comments
t1
0
0
0
t2
0
0
0
t3
70
90
100
t4
10
10
10
t5
95
120
150
NOTES
1Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, tR = tF = 5 ns.
2Timing measurement reference level is V INH + V INL
2
ns min
ns min
ns min
ns min
ns min
Address to WR Setup Time
Address to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Write Pulse Width
INTERFACE LOGIC INFORMATION
Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
Table I. AD7228A Truth Table
AD7228A Control Inputs
WR
A2
A1
A0
H
X
X
X
L
L
L
L
g
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
AD7228A
Operation
No Operation
Device Not Selected
DAC 1 Transparent
DAC 1 Latched
DAC 2 Transparent
DAC 3 Transparent
DAC 4 Transparent
DAC 5 Transparent
DAC 6 Transparent
DAC 7 Transparent
DAC 8 Transparent
Figure 1. Input Control Logic
H = High State L = Low State X = Don’t Care
REV. A
Figure 2. Write Cycle Timing Diagram
–3–
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