AD7280A 查看數據表（PDF） - Analog Devices
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AD7280A Datasheet PDF : 48 Pages
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AD7280A
Parameter
REGULATOR OUTPUT (VREG)
Input Voltage Range
Output Voltage, VREG13
Output Current14
Line Regulation
Load Regulation
Internal Short Protection Limit
CELL BALANCING OUTPUTS15
Output High Voltage, VOH
Output Low Voltage, VOL
CB1 Output Ramp-Up Time16
CB1 Output Ramp-Down Time17
CB2 to CB6 Output Ramp-Up Time16
CB2 to CB6 Output Ramp-Down Time17
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance
Output Coding
Min
Typ
Max
8
30
4.9
5.2
5.5
5
0.5
2.5
25
VREG − 1
5
0
30
30
380
30
VREG + 0.2
2.4
0.4
±10
5
VDRIVE × 0.9
0.4
±10
5
Straight binary
Unit
V
V
mA
mV/V
mV/mA
mA
V
V
μs
μs
μs
μs
V
V
μA
pF
V
V
μA
pF
Test Conditions/Comments
5 mA external load
For a 10 Ω short
ISOURCE = 415 nA
For an 80 pF load
For an 80 pF load
For an 80 pF load
For an 80 pF load
ISOURCE = 200 μA
ISINK = 200 μA
1 For dc accuracy specifications, the LSB size for cell voltage measurements is (2 × VREF − 1 V)/4096. The LSB size for auxiliary ADC input voltage measurements is (2 × VREF)/4096.
2 ADC unadjusted error includes the INL of the ADC and the gain and offset errors of the VIN0 to VIN6 input channels.
3 The conversion accuracy during cell balancing is decreased due to the activation of the cell balance circuitry. The ADC unadjusted error increases by a factor of 4.
4 Total unadjusted error includes the INL of the ADC and the gain and offset errors of the VIN0 to VIN6 input channels, as well as the reference error, that is, the difference between
the ideal and actual reference voltage and the temperature coefficient of the 2.5 V reference.
5 The conversion accuracy during cell balancing is decreased due to the activation of the cell balance circuitry. The total unadjusted error increases by a factor of 4.
6 For the full analog input range, that is, 1 V to 2 × VREF, the total unadjusted error increases by 20%.
7 The total current measured on the input pins while converting is the sum of the static and dynamic leakage currents. See the Terminology section.
8 Bit D3 of the control register is set to 0 (thermistor termination resistor function is not in use).
9 ADC unadjusted error includes the INL of the ADC and the gain and offset errors of the AUXx input channels.
10 Total unadjusted error includes the INL of the ADC and the gain and offset errors of the AUXx input channels, as well as the reference error, that is, the difference between the
ideal and actual reference voltage and the temperature coefficient of the 2.5 V reference.
11 The turn-on settling time is the time from the rising edge of the PD signal until the conversion result settles to the specified accuracy. This includes the time required
to power up the regulator and the reference. Note that a rising edge on the CNVST input is also required to power up the reference. This rising edge should occur after
the rising edge on PD.
12 Sample tested during initial release to ensure compliance.
13 The regulator output voltage is specified with an external 5 mA load in addition to the current required to drive the AVCC, DVCC, and VDRIVE supplies of the AD7280A.
14 This specification refers to the maximum regulator output current that is available for external use.
15 The CBx outputs can be set to 0 V or VREG with respect to the negative terminal of the cell being balanced.
16 The CB1 to CB6 output ramp-up times are defined from the rising edge of the CS command until the CB output exceeds VREG − 1 V with respect to the negative
terminal of the cell being balanced.
17 The CB1 to CB6 output ramp-down times are defined from the rising edge of the CS command until the CB output falls below 50 mV with respect to the negative
terminal of the cell being balanced.
Rev. 0 | Page 4 of 48
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