AD7298BCPZ-RL7(RevPrA) 查看數據表（PDF） - Analog Devices
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AD7298BCPZ-RL7 Datasheet PDF : 18 Pages
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Preliminary Technical Data
AD7298
TIMING SPECIFICATIONS
VDD = 2.8V to 3.6V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal/external; TA = −40°C to + 125°C, unless otherwise noted. 7
Table 3.
Parameter
tCONVERT
fSCLK
tQUIET
Limit at TMIN, TMAX
16 × tSCLK
1
100
50
20
TBD
TBD
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
tPOWER-
UP_PARTIAL
tPOWER-UP
10
25
TBD
0.4 × tSCLK
0.4 × tSCLK
TBD
15/45
10
5
TBD
TBD
TBD
Unit
µs max
µs max
µs max
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns
min/max
ns min
ns min
ns min
μs max
Test Conditions/Comments
Conversion time
For each ADC channel VIN0 to VIN7, FSCLK = 20MHz
For Temperature Sensor channel
Frequency of external serial clock
Frequency of external serial clock
Minimum quiet time required between the end of serial read and the start of the next
voltage conversion in repeat and non-repeat mode.
Minimum quiet time required between the end of serial read and the start of the next
temperature conversion, for consecutive Temperature conversions.
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulsewidth
SCLK high pulsewidth
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
TSENSEBUSY falling edge to CS falling edge
Power-up time from partial power-down
μs max Power-up time from full power-down
7 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
Rev. PrA | Page 4 of 18
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