AD7490BRU(RevA) 查看數據表（PDF） - Analog Devices
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AD7490BRU Datasheet PDF : 24 Pages
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AD7490–SPECIFICATIONS (VDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK1 = 20 MHz, TA = TMIN to TMAX, unless
otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
Signal to Noise +1 Distortion (SINAD)3
Signal to Noise Ratio (SNR)3
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation3
Full Power Bandwidth
DC ACCURACY3
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to VREF IN Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 ϫ VREF IN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN4
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
B Version2 Unit
69
dB min
68
dB min
69.5
dB min
–74
dB max
–71
dB max
–75
dB max
–73
dB max
–85
dB typ
–85
dB typ
10
ns typ
50
ps typ
–82
dB typ
8.2
MHz typ
1.6
MHz typ
12
±1
–0.95/+1.5
±8
± 0.5
±2
± 0.6
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
±2
LSB max
± 0.5
LSB max
±8
LSB max
± 0.5
LSB max
±1
LSB max
± 0.5
LSB max
0 to REFIN
V
0 to 2 ϫ REFIN V
±1
µA max
20
pF typ
2.5
V
±1
µA max
36
kΩ typ
0.7 ϫ VDRIVE
0.3 ϫ VDRIVE
±1
10
V min
V max
µA max
pF max
VDRIVE – 0.2
0.4
V min
V max
± 10
µA max
10
pF max
Straight (Natural) Binary
Twos Complement
Test Conditions/Comments
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
@ 5 V, 70.5 dB typ
@ 3 V, 69.5 dB typ
@ 5 V, –84 dB typ
@ 3 V, –77 dB typ
@ 5 V, –86 dB typ
@ 3 V, –80 dB typ
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
± 0.6 LSB typ
–VREF IN to +VREF IN Biased about VREF with
Twos Complement Output Coding Offset
± 0.6 LSB typ
RANGE Bit Set to 1
RANGE Bit Set to 0,
VDD/VDRIVE = 4.75 V to 5.25 V for 0 to 2 ϫ REFIN
± 1% Specified Performance
fSAMPLE = 1 MSPS
Typically 10 nA, VIN 5 0 V or VDRIVE
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
Weak/Tri Bit Set to 0
Weak/Tri Bit Set to 0
Coding Bit Set to 1
Coding Bit Set to 0
–2–
REV. A
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