AD7490 查看數據表（PDF） - Analog Devices
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AD7490 Datasheet PDF : 29 Pages
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AD7490
Data Sheet
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN+3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD 4
Normal Mode (Static)
Normal Mode (Operational)
(fS = Maximum Throughput)
Auto Standby Mode
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
Auto Standby Mode (Static)
Auto Shutdown Mode (Static)
Full Shutdown Mode
Test Conditions/Comments
VIN = 0 V or VDRIVE
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
WEAK/TRI bit set to 0
WEAK/TRI bit set to 0
Coding bit set to 1
Coding bit set to 0
16 SCLK cycles, SCLK = 20 MHz
Sine wave input
Full-scale step input
VDD = 5 V (see the Serial Interface
section)
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 500 kSPS
Static
fSAMPLE = 250 kSPS
Static
SCLK on or off
VDD = 5 V, fSCLK = 20 MHz
VDD = 3 V, fSCLK = 20 MHz
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Min
Typ
Max
Unit
0.7 × VDRIVE
±0.01
V
0.3 × VDRIVE V
±1
µA
10
pF
VDRIVE − 0.2
V
0.4
V
±10
µA
10
pF
Straight (Natural) Binary
Twos Complement
800
ns
300
ns
300
ns
1
MSPS
2.7
2.7
600
1.55
960
0.02
5.25
V
5.25
V
µA
2.5
mA
1.8
mA
mA
100
µA
µA
0.5
µA
0.5
µA
12.5
mW
5.4
mW
460
µW
276
µW
2.5
µW
1.5
µW
2.5
µW
1.5
µW
1 Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section.
2 See the Terminology section.
3 Guaranteed by characterization.
4 See the Power vs. Throughput Rate section.
Rev. D | Page 4 of 28
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